Program

Technical Program

All times shown in Pacific Standard Time (UTC-8).

All events in the San Carlos II-IV rooms and in the foyer, unless indicated otherwise.

Sunday, February 12, 2023

Workshops and Tutorials are listed separately. All workshops and tutorials are included in the conference fee, but may require separate registration in order to manage capacity. Check each event for additional registration requirements.

There is a 6:00pm Reception for all attendees in the San Carlos Ballroom Foyer.

Monday, February 13, 2023

★ indicates best paper candidate

9:00 am – 9:10 am	Opening
9:10 am – 10:00 am	Keynote: Compiler Support for Structured Data Saman Amarasinghe, MIT
10:00 am – 10:15 am	Break
10:15 am – 11:30 am	Paper Session 1 – High-Level Abstraction and Tools Chair: George Constantinides, Imperial College London
	DONGLE: Direct FPGA-Orchestrated NVMe Storage for HLS★ (Best Paper Award) Linus Y. Wong, Jialiang Zhang and Jing "Jane" Li (University of Pennsylvania)
	FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs    Linfeng Du, Tingyuan Liang (Hong Kong University of Science and Technology), Sharad Sinha (Indian Institute of Technology Goa), Zhiyao Xie and Wei Zhang (Hong Kong University of Science and Technology)
	Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking    Jiahui Xu, Emmet Murphy (ETH Zurich), Jordi Cortadella (UPC Barcelona) and Lana Josipović (ETH Zurich)
	Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits (short paper)    Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri (EPFL), Lana Josipović (ETH Zurich) and Paolo Ienne (EPFL)
11:30 am – 12:30 pm	Poster Session 1
12:30 pm – 2:00 pm	Lunch Ferrantes Bay View Ballroom
2:00 pm – 3:15 pm	Paper Session 2 – Applications and Design Studies 1 Chair: Jeffrey Goeders, Brigham Young University
	A Study of Early Aggregation in Database Query Processing on FPGAs Mehdi Moghaddamfar (TU Dresden & SAP SE), Norman May (SAP SE), Christian Färber (Intel), Wolfgang Lehner and Akash Kumar (TU Dresden)
	FNNG: A High-Performance FPGA-based Accelerator for K-Nearest Neighbor Graph Construction Chaoqiang Liu, Haifeng Liu, Long Zheng, Yu Huang, Xiangyu Ye, Xiaofei Liao and Hai Jin (Huazhong University of Science and Technology)
	ACTS: A Near-Memory FPGA Graph Processing Framework Wole Jaiyeoba and Kevin Skadron (University of Virginia)
	Exploring the Versal AI Engines for Accelerating Stencil-based Atmospheric Advection Simulation (short paper) Nick Brown (EPCC, at the University of Edinburgh)
3:15 pm – 3:30 pm	Break
3:30 pm – 5:00 pm	Paper Session 3 – Architecture, CAD, and Circuit Design Chair: Raymond Nijssen, Achronix
	Regularity Matters: Designing Practical FPGA Switch-Blocks    Stefan Nikolić and Paolo Ienne (EPFL)
	Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters★ Colin Drewes, Olivia Weng, Keegan Ryan (UCSD), Bill Hunter, Christopher McCarty (Georgia Tech Research Institute), Ryan Kastner (UCSD) and Dustin Richmond (UCSC)
	Post-Radiation Fault Analysis of a High Reliability FPGA Linux SoC Andrew Wilson, Nate Baker, Ethan Campbell, Jackson Sahleen and Mike Wirthlin (Brigham Young University)
	FPGA Technology Mapping with Adaptive Gate Decomposition (short paper) Longfei Fan and Chang Wu (Fudan University)
	Accurate Estimation of FPGA Routing Mux Usage and Routability Without Explicit Routing (short paper) Jonathan W. Greene (UC Berkeley and Cambios Computing LLC)
5:00 pm – 6:30 pm	Adjourn
5:10 pm – 6:00 pm	Steering Committee Meeting Los Angeles Room
6:30 pm – 8:30 pm	Banquet and Invited Panel on "Open-source and FPGAs: Hardware, Software, Both or None?" San Carlos Ballroom

Tuesday, February 14, 2023

★ indicates best paper candidate

9:00 am – 9:10 am	Chair's Announcement
9:10 am – 10:00 am	Keynote: FPGAs and Their Evolving Role in Domain Specific Architectures: A Case Study of the AMD 400G Adaptive SmartNIC/DPU SoC Jaideep Dastidar, AMD
10:00 am – 10:55 am	Paper Session 4 – Deep Learning Chair: Mohamed Abdelfattah, Cornell Tech
	CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture    Jinming Zhuang (University of Pittsburgh), Jason Lau (UCLA), Hanchen Ye (UIUC), Zhuoping Yang, Yubo Du (University of Pittsburgh), Jack Lo, Kristof Denolf, Stephen Neuendorffer (AMD), Alex Jones, Jingtong Hu (University of Pittsburgh), Deming Chen (UIUC), Jason Cong (UCLA) and Peipei Zhou (University of Pittsburgh)
	Approximate Hybrid Binary-Unary Computing with Applications in BERT Language Model and Image Processing Alireza Khataei, Gaurav Singh and Kia Bazargan (University of Minnesota)
	Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search (short paper) Lei Cai, Jing Wang, Lianfeng Yu, Bonan Yan, Yaoyu Tao and Yuchao Yang(Peking University)
10:55 am – 11:10 pm	Break
11:10 am – 12:30 pm	Paper Session 5 – FPGA-Based Computing Engines Chair: Peipei Zhou, University of Pittsburgh
	hAP: A Spatial-von Neumann Heterogeneous Automata Processor with Optimized Resource and IO Overhead on FPGA Xuan Wang, Lei Gong, Jing Cao, Wenqi Lou (University of Science and Technology of China), Weiya Wang (Boston University), Chao Wang and Xuehai Zhou (University of Science and Technology of China), Weiya Wang (University of Science and Technology of China)
	CSAIL2019 Crypto-Puzzle Solver Architecture★ Sergey Gribok, Martin Langhammer and Bogdan Pasca (Intel)
	ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration Kan Shi (Institute of Computing Technology, Chinese Academy of Sciences), Shuoxiang Xu (ShanghaiTech University), Yuhan Diao (Imperial College London), David Boland (The University of Sydney), Yungang Bao (Institute of Computing Technology, Chinese Academy of Sciences)
	BOBBER A Prototyping Platform for Batteryless Intermittent Accelerators (short paper)    Vishak Narayanan, Rohit Sahu, Jidong Sun and Henry Duwe (Iowa State University)
12:30 pm – 2:00 pm	Lunch Ferrantes Bay View Ballroom
2:00 pm – 3:00 pm	Poster Session 2
3:00 pm – 4:10 pm	Paper Session 6 – Applications and Design Studies 2 Chair: Jing (Jane) Li, University of Pennsylvania
	A Framework for Monte-Carlo Tree Search on CPU-FPGA Heterogeneous Platform via On-Chip Dynamic Tree Management Yuan Meng (USC), Rajgopal Kannan (US Army Research Lab), Viktor K Prasanna (USC)
	Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver    Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi (UCLA), Robert F. Lucas (Ansys), Jason Cong (UCLA)
	Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA Sasindu Wijeratne, Ta-Yang Wang (USC), Rajgopal Kannan (US Army Research Lab), Viktor Prasanna (USC)
4:10 pm – 4:30 pm	Best Paper Award and Closing Remarks

Poster Session 1 (February 13)

11:30am – 12:30pm

Title	Authors
OMT: A Demand-Adaptive, Hardware-Targeted Bonsai Merkle Tree Framework for Embedded Heterogeneous Memory Platform	Raki Shadab, Yu Zou, Sanjay Gandham and Mingjie Lin (University of Central Florida)
Cyclone-NTT: An NTT/FFT Architecture Using Quasi-Streaming of Large Datasets on DDR- and HBM-based FPGA Platforms	Kaveh Aasaraai (Jump Trading), Emanuele Cesena, Rahul Maganti, Nicolas Stalder (Jump Crypto), Javier Varela and Kevin Bowers (Jump Trading)
AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture	Hyeong-Ju Kang (Korea University of Technology and Education)
Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the International Space Station	Tim Oberschulte, Jakob Marten and Holger Blume (Institute of Microelectronic Systems, Leibniz University Hannover)
Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization	Meghna Mandava and Deming Chen (University of Illinois, Urbana-Champaign)
Graph-OPU: An FPGA-Based Overlay Processor for Graph Neural Networks	Ruiqi Chen (Fudan University), Yuhanxiao Ma (New York University), Enhao Tang, Shun Li (Fuzhou University), Yanxiang Zhu (VeriMake Innovation Lab), Haoyang Zhang, Jun Yu and Kun Wang (Fudan University)
Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits	Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri (EPFL), Lana Josipović (ETH Zurich) and Paolo Ienne (EPFL)
HMLib: Efficient Data Transfer for HLS using Host Memory	Michael Lo (UCLA), Young-kyu Choi (Inha University), Weikang Qiao, Mau-Chung Chang and Jason Cong (UCLA)
An Efficient High-Speed FFT Implementation	Ross Martin (Bit by Bit Signal Processing LLC)
Weave: Abstraction for Accelerator Integration of Generated Modules	Tuo Dai, Bizhao Shi and Guojie Luo (Peking University)
A Novel FPGA Simulator Accelerating Reinforcement Learning-Based Design of Power Converters	Zhenyu Xu, Miaoxiang Yu, Qing Yang, Yeonho Jeong and Tao Wei (The University of Rhode Island)
A Fractal Astronomical Correlator based on FPGA Cluster with Scalability	Lin Shu, Long Xiao, Yafang Song, Qiuxiang Fan (Institute of Automation, Chinese Academy of Sciences), Guitian Fang (Guangdong Institute of Artificial Intelligence and Advanced Computing) and Jie Hao(Institute of Automation, Chinese Academy of Sciences)
Power Side-channel Countermeasures for ARX Ciphers using High-level Synthesis	Saya Inagaki, Mingyu Yang (Tokyo Institute of Technology), Yang Li, Kazuo Sakiyama (The University of Electro-Communications, Tokyo) and Yuko Hara-Azumi (Tokyo Institute of Technology)
Single-Batch CNN Training using Block Minifloats on FPGAs	Chuliang Guo, Binglei Lou, Xueyuan Liu, David Boland and Philip Leong (The University of Sydney)

Poster Session 2 (February 14)

2:00pm – 3:00pm

Title	Authors
FPGA Technology Mapping with Adaptive Gate Decomposition	Longfei Fan and Chang Wu (Fudan University)
Accelerating Neural-ODE Inference on FPGAs with Two-Stage Structured Pruning and History-based Stepsize Search	Lei Cai, Jing Wang, Lianfeng Yu, Bonan Yan, Yuchao Yang and Yaoyu Tao (Peking University)
BOBBER A Prototyping Platform for Batteryless Intermittent Accelerators	Vishak Narayanan, Rohit Sahu, Jidong Sun and Henry Duwe (Iowa State University)
Accurate Estimation of FPGA Routing Mux Usage and Routability Without Explicit Routing	Jonathan Greene (UC Berkeley and Cambios Computing LLC)
Adapting Skip Connections for Resource-Efficient FPGA Inference	Olivia Weng, Gabriel Marcano (UCSD), Vladimir Loncar (MIT), Alireza Khodamoradi (AMD), Nojan Sheybani, Farinaz Koushanfar (UCSD), Kristof Denolf (Xilinx), Javier Duarte and Ryan Kastner (UCSD)
Multi-bit-width CNN Accelerator with Systolic-in-Systolic dataflow and Single DSP Multiple Multiplication Scheme	Mingqiang Huang, Yucen Liu, Sixiao Huang, Kai Li, Qiuping Wu and Hao Yu (Southern University of Science and Technology)
Janus: An Experimental Reconfigurable SmartNIC with P4 Programmability and SDN Isolation	Bharat Sukhwani, Mohit Kapur, Alda Sanomiya, Liran Schour, Martin Ohmacht, Chris Ward, Chuck Haymes and Sameh Asaad (IBM Research)
LAWS: Large-Scale Accelerated Wave Simulations on FPGAs	Dimitrios Gourounas, Bagus Hanindhito (UT Austin), Arash Fathi, Dimitar Trenev (ExxonMobil), Lizy John and Andreas Gerstlauer (UT Austin)
Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing	Shashwat Shrivastava, Stefan Nikolić (EPFL), Chirag Ravishankar, Dinesh Gaitonde (AMD) and Mirjana Stojilović (EPFL)
Towards a Machine Learning Approach to Predicting the Difficulty of FPGA Routing Problems	Andrew Gunter and Steve Wilton (University of British Columbia)
An FPGA-Based Weightless Neural Network for Edge Network Intrusion Detection	Zachary Susskind, Aman Arora (UT Austin), Alan Bacellar, Diego Dutra (Federal University of Rio de Janeiro), Igor Miranda (Federal University of Recôncavo da Bahia), Mauricio Breternitz Jr. (ISCTE - Lisbon University Institute), Priscila Lima (COPPE/UFRJ), Felipe França (Institute of Telecommunications and Federal University of Rio de Janeiro), Lizy John (UT Austin)
A Flexible Toolflow for Mapping CNN Models to High Performance FPGA-based Accelerators	Yongzheng Chen and Gang Wu (School of Computer Science and Engineering, Northeastern University, China)
Exploring the Versal AI Engines for Accelerating Stencil-based Atmospheric Advection Simulation	Nick Brown (EPCC, at the University of Edinburgh)
Senju: A Framework for the Design of Highly Parallel FPGA-based Iterative Stencil Loop Accelerators	Emanuele Del Sozzo (RIKEN Center for Computational Science), Davide Conficconi (Politecnico di Milano), Marco Santambrogio (Politecnico di Milano) and Kentaro Sano (RIKEN Center for Computational Science)
FPGA Acceleration for Sequential Interference Cancellation in Severe Multipath Acoustic Communication Channels	Jinfeng Li and Yahong Zheng (Lehigh University)
FreezeTime: Towards System Emulation through Architectural Virtualization	Sergiu Mosanu, Joshua Fixelle, Kevin Skadron and Mircea Stan (University of Virginia)