| Sunday, February 24, 2008 | |||
| 2:00 PM | Pre-conference Workshop (Co-Chairs: Guy Lemieux, University of British Columbia and Tarek El-Ghazawi, The George Washington University) | ||
| Designing with Extreme Parallelism | |||
| Reception | |||
| 6:00 PM | Registration | ||
| 7:00 PM | Welcome Reception | ||
| Monday, February 25, 2008 | |||
| 8:00 AM | Continental Breakfast | ||
| Registration | |||
| 8:40 AM | Opening Remarks | ||
| 9:00 AM | Session 1: Physical Design (Chair: Jason Cong, UCLA) | ||
| Architecture-Specific Packing for Virtex-5 FPGAs [PPT] Taneem Ahmed, Paul Kundarewich, Jason Anderson, Brad Taylor and Rajat Aggarwal Xilinx, Inc. |
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| High-Quality, Deterministic Parallel
Placement for FPGAs on Commodity Hardware [PPT] Adrian Ludwin, Vaughn Betz and Ketan Padalia Altera Corp. |
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| Enforcing Long-Path Timing Closure for
FPGA Routing with Path Searches on Clamped Lexicographic Spirals [PPT] Keith So University of New South Wales |
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| 10:00 AM | Poster Session 1: Architecture and CAD (Chair: Kia Bazargan, University of Minnesota) | ||
| 11:00 AM | Session 2: Technology Mapping (Chair: Deming Chen, University of Illinois at Urbana-Champaign) | ||
| Beyond the arithmetic constraint:
depth-optimal mapping of logic chains in LUT-based FPGAs [PPT] Michael Frederick and Arun Somani Iowa State University |
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| WireMap: FPGA
Technology Mapping for Improved Routability [PPT] Stephen Jang, Billy Chan, Kevin Chung and Alan Mishchenko Xilinx, Inc. and University of California, Berkeley |
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| Mapping for
Better Than Worst-Case Delays In LUT-Based FPGA Designs [PPT] Jason Cong and Kirill Minkovich University of California, Los Angeles |
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| Noon | Lunch | ||
| 2:00 PM | Session 3: Simulation Acceleration (Chair: John Wawrzynek, UC Berkeley) | ||
| Lithographic Aerial Image Simulation
with FPGA-Based Hardware Acceleration [PPT] Jason Cong and Yi Zou University of California, Los Angeles |
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| A
Complexity-Effective Architecture for Accelerating Full-System Multiprocessor
Simulations using FPGAs [PPT] Eric Chung, Eriko Nurvitadhi, James Hoe, Ken Mai and Babak Falsafi Carnegie Mellon University and École Polytechnique Fédérale de Lausanne |
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| A-Ports: An
Efficient Abstraction for Cycle-Accurate Performance Models on FPGAs [PPT] Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Joel Emer and Arvind MIT and Intel Corporation |
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| 3:00 PM | Poster Session 2: Computing with Reconfigurable Technology (Chair: Mike Wirthlin, Brigham Young University) | ||
| 4:00 PM | Session 4: Synthesis at Higher-Level Abstractions (Chair: Satnam Singh, Microsoft Cambridge Research) | ||
| Efficient ASIP Design for Configurable
Processors with Fine-Grained Resource Sharing Quang Dinh, Deming Chen and Martin Wong University of Illinois at Urbana-Champaign |
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| Pattern-Based
Behavior Synthesis for FPGA Resource Reduction Jason Cong and Wei Jiang University of California, Los Angeles |
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| C is for
Circuits: Capturing FPGA Circuits as Sequential Code for Portability Scott Sirowy, Greg Stitt and Frank Vahid University of California, Riverside and University of Florida |
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| 5:30 PM | Steering Committee Meeting: Big Sur Room | ||
| 7:00 PM | Dinner and Evening
Panel (Co-Chairs: Tarek El-Ghazawi,
The George Washington University and Guy Lemieux , University of British Columbia) |
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| Extreme Parallel Architectures for the Masses | |||
| Tuesday, February 26, 2008 | |||
| 8:00 AM | Continental Breakfast | ||
| Registration | |||
| 8:50 AM | Session 5: Architecture Tools (Chair: Steve Trimberger, Xilinx) | ||
| TORCH: A Design Tool for Routing
Channel Segmentation in FPGAs Mingjie Lin and Abbas El Gamal Stanford University |
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| Modeling FPGA
Routing Demand in Early-Stage Architecture Development Wei Mark Fang and Jonathan Rose University of Toronto |
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| Area and Delay
Trade-offs in the Circuit and Architecture Design of FPGAs [PDF] Ian Kuon and Jonathan Rose University of Toronto |
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| Trace-Based Framework
for Concurrent Development of Process and FPGA Architecture Considering
Process Variation and Reliability [PPT] Lerong Cheng, Yan Lin, Lei He and Yu Cao University of California, Los Angeles and Arizona State University |
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| 10:10 AM | Poster Session 3: Applications and Implementations (Chair: Mike Hutton, Altera) | ||
| 11:10 AM | Session 6: Architecture (Chair: Guy Lemieux, University of British Columbia) | ||
| A Novel FPGA Logic Block for Improved
Arithmetic Performance [PPT] Hadi Parandeh-Afshar, Philip Brisk and Paolo Ienne École Polytechnique Fédérale de Lausanne (EPFL) |
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| Architectural
Improvements for Field Programmable Counter Arrays: Enabling Efficient
Synthesis of Fast Compressor Trees on FPGAs [PPT] Alessandro Cevrero, Pangiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Verma, Philip Brisk, Frank Gurkaynak, Yusuf Leblebici and Paolo Ienne École Polytechnique Fédérale de Lausanne (EPFL) |
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| The Amorphous
FPGA Architecture Mingjie Lin Stanford University |
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| 12:10 PM | Lunch | ||
| 1:40 PM | Session 7: Reconfigurable Computing (Chair: Peter Cheung, Imperial College London) | ||
| Reconfigurable Computing for Learning
Bayesian Networks Narges Bani Asadi, Teresa H. Meng and Wing H. Wong Stanford University |
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| HybridOS: Runtime
Support for Reconfigurable Accelerators [PDF] John Kelm and Steve Lumetta University of Illinois at Urbana-Champaign |
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| Vector Processing
as a Soft-core CPU Accelerator [PPT] Jason Yu, Guy Lemieux and Christopher Eagleston University of British Columbia |
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| 2:40 PM | Break | ||
| 3:10 PM | Session 8: Random Number Generators (Chair: Steve Neuendorffer, Xilinx) | ||
| FPGA-optimised high-quality uniform
random number generators David Barrie Thomas and Wayne Luk Imperial College London |
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| A Hardware
Framework for Fast Generation of Multiple Long-period Random Number Streams Ishaan Dalal and Deian Stefan The Cooper Union |
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| 3:50 PM | Closing Remarks | ||
| Poster Sessions | |||
| Monday, February 25, 2008 | |||
| 10:00 AM | Poster Session 1: Architecture and CAD (Chair: Kia Bazargan, University of Minnesota) | ||
| Efficient Tiling Patterns for Reconfigurable Gate Arrays Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst and Sylvain Guilley École Nationale Supérieure des Télécommunications |
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| FPGA
Interconnect Design using Logical Effort Haile Yu, Yuk Hei Chan and Philip Leong The Chinese University of Hong Kong |
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| Speed and Yield Enhancement by Track Swapping on Critical
Paths Utilizing Random Variations for FPGAs Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi and Hidetoshi Onodera Kyoto University |
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| Measuring and Modelling FPGA Clock Variability Pete Sedcole, Justin S J Wong and Peter Y K Cheung Imperial College London |
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| High-Throughput Interconnect Wave-Pipelining for Global
Communication in FPGAs Terrence S.T. Mak, Pete Sedcole, Justin Wong, Peter Y.K. Cheung and Wayne Luk Imperial College London |
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| Configurable Decoders with Applications
in Fast Partial Reconfiguration of FPGAs Matthew Jordan and Ramachandran Vaidyanathan Intergraph Corp. and Louisiana State University |
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| 3:00 PM | Poster Session 2: Computing with Reconfigurable Technology (Chair: Mike Wirthlin, Brigham Young University) | ||
| When FPGAs are Better at Floating-Point than
Microprocessors Florent de Dinechin, Jeremie Detrey, Octavian Cret and Radu Tudoran École Normale Supérieure de Lyon and Technical University of Cluj-Napoca |
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| Efficient FPGA Implementation of QR Decomposition Using a
Systolic Array Architecture Xiaojun Wang and Miriam Leeser Northeastern University |
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| An Integrated Debugging Environment for FPGA-based
Computing Systems Kevin Camera and Bob Brodersen University of California, Berkeley |
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| CHiMPS: High-level Compilation Flow for Hybrid CPU-FPGA
Architectures Andrew Putnam, Dave Bennett, Eric Dellinger, Jeff Mason and Prasanna Sundararajan University of Washington and Xilinx |
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| Retrieving 3-D information with FPGA-based Stream
Processing Hidenori Matsubayashi, Shinsuke Nino, Toru Aramaki, Yuichiro Shibata and Kiyoshi Oguri Nagasaki University |
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| Communication Bottleneck in Hardware-Software Partitioning Maryam Moazeni, Alireza Vahdatpour, Karthik Gururaj and Majid Sarrafzadeh University of California, Los Angeles |
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| A Type System for Static Typing of a Domain-Specific
Language Paul McKechnie, Nathan Lindop and Wim Vanderbauwhede Institute for System Level Integration, Xilinx, and University of Glasgow |
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| Tuesday, February 26, 2008 | |||
| 10:10 AM | Poster Session 3: Applications and Implementations (Chair: Mike Hutton, Altera) | ||
| FPGA Based Multiple-Channel Vibration
Analyzer for Industrial Applications with Reconfigurable Post-processing
Capabilities for Automatic Failure Detection on Machinery Luis Miguel Contreras-Medina, Rene Romero-Troncoso, Jose Rangel-Magdaleno and Jesus Millan-Almaraz Universidad de Guanajuato |
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| FPGA Implementation of
a Novel Algorithm for on-line Bar Breakage Detection on Induction Motors Jose de Jesus Rangel-Magdaleno, Rene de Jesus Romero-Troncoso, Luis Miguel Contreras-Medina and Arturo Garcia-Perez Universidad de Guanajuato |
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| Implementing
High-Speed String Matching Hardware for Network Intrusion Detection Systems Atul Mahajan, Benfano Soewito, Sai Kumar Parsi, Ning Weng and Haibo Wang Southern Illinois University |
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| FPGA-Based Data
Acquisition System for a Positron Emission Tomography Scanner Michael Haselman, Scott Hauck, Robert Miyaoka and Thomas Lewellen University of Washington |
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| A Pipelined
Binary Tree as a Case Study on Designing Efficient Circuits for an FPGA in a
BRAM Aware Design David Sheldon and Frank Vahid University of California, Riverside |
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| From the
Bitstream to the Netlist Jean-Baptiste Note and Eric Rannaud École Normale Supérieure |
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| Flexible
FPGA-Based Parallel Architecture for Identification of Repetitive Sequences
in Interleaved Pulse Trains Amin Ansari and Keyvan Amiri University of Michigan and Rice University |
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| 10:10 AM | Poster Session 3: Posters from Paper Presentations | ||
| A Complexity-Effective Architecture for Accelerating Full-System
Multiprocessor Simulations using FPGAs Eric Chung, Eriko Nurvitadhi, James Hoe, Ken Mai and Babak Falsafi Carnegie Mellon University and École Polytechnique Fédérale de Lausanne |
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| Vector Processing as a Soft-core CPU
Accelerator Jason Yu, Guy Lemieux and Christopher Eagleston University of British Columbia |