Note: Breakfast at hotel is 7am to 10:30am on weekends and 6am to 9am on weekdays.
| Time | |
|---|---|
| Sunday February 23 | |
| 8:00 | Session: Invited Tutorials |
| 8:00 | Vitis Introduction: Edge and Cloud Acceleration Workflow |
| Parimal Patel | |
| 8:30 | From C/C++ to Dynamically Scheduled Circuits |
| Lana Josipović (EPFL), Andrea Guerrieri (EPFL); Paolo Ienne (EPFL) | |
| 9:30 | FPGA Hardware Security for Datacenters and Beyond |
| Kaspar Matas(The University of Manchester); Tuan La(The University of Manchester); Nikola Grunchevski(The University of Manchester); Khoa Pham(The University of Manchester); Dirk Koch(University of Manchester) | |
| 11:30 | Lunch |
| 12:45 | Invited Session: Security in FPGA Design and Application (Chair: Ryan Kastner, University of California, San Diego; and Russell Tessier, University of Massachusetts) |
| 12:45 | Establishing trust in Microelectronics |
| Lee Lerner (Georgia Tech) | |
| 13:00 | Thermal and Voltage Side Channels and Attacks in Cloud FPGAs |
| Jakub Szefer (Yale University) | |
| 13:15 | Multi-tenant FPGA Security: Challenges and Opportunities |
| Patrick Koeberl (Intel Corporation) | |
| 13:30 | FPGA/SoC Security: Arms Race in the Cloud |
| Steve McNeil (Xilinx) | |
| 13:45 | Panel Discussion |
| 14:15 | Coffee Break |
| 14:30 | Invited Panel: What to do with Datacenter FPGAs Besides Deep Learning (Chair: Andrew Putnam, Microsoft) |
| 16:00 | Close for the day |
| 16:00 | FCCM PC Meeting |
| 19:30 | Reception |
| Monday February 24 | |
| 8:00 | Open the conference (General Chair/Program Chair) |
| 8:15 | Keynote: Symbiosis in Action: Reconfigurable Architectures and EDA (Chair: Lesley Shannon, Simon Fraser University) |
| Mahesh Iyer (Intel) | |
| 8:45 | Session: High-Level Abstractions and Tools I (Chair: Caiwen Ding, University of Connecticut) |
| 8:45 | Maximizing the Serviceability of Partially Reconfigurable FPGA Systems in Multi-tenant Environment |
| Tuan D. A. Nguyen(Technische Universität Dresden); Akash Kumar(Technische Universitaet Dresden) | |
| 9:10 | AutoDNNchip: An Automated DNN Chip Generator through Compilation, Optimization, and Exploration |
| Pengfei Xu(Rice University); Yang Zhao(Rice University); Xiaofan Zhang(University of Illinois at Urbana-Champaign); Cong Hao(University of Illinois Urbana-Champaign); Zetong Guan(Rice University); Yongan Zhang(Rice University); Yue Wang(Rice University); Deming Chen(University of Illinois Urbana-Champaign); Yingyan Lin(Rice University) | |
| 9:35 | HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration |
| Jiajie Li(Tsinghua University); Yuze Chi(University of California, Los Angeles); Jason Cong(UCLA) | |
| 9:40 | Fingerprinting Cloud FPGA Infrastructures |
| Shanquan Tian(Yale University); Wenjie Xiong(Yale University); Ilias Giechaskiel(University of Oxford); Kasper Rasmussen(University of Oxford); Jakub Szefer(Yale University) | |
| 9:45 | Poster Session I (Chair: Vaughn Betz, University of Toronto) |
| 10:55 | Session: Appications I (Chair: Miriam Leeser, Northeastern University) |
| 10:55 | Massively Simulating Adiabatic Bifurcations with FPGA to Solve Combinatorial Optimization |
| Yu Zou(University of Central Florida); Mingjie Lin(University of Central Florida) | |
| 11:20 | High-performance FPGA network switch architecture |
| Philippos Papaphilippou(Imperial College London); Jiuxi Meng(Imperial College London); Wayne Luk(Imperial College) | |
| 11:45 | Using OpenCL to Enable Software-like Development of an FPGA-Accelerated Biophotonic Cancer Treatment Simulator |
| Tanner Young-Schultz(University of Toronto); Lothar Lilge(Princess Margaret Cancer Centre); Stephen Brown(University of Toronto); Vaughn Betz(University of Toronto) | |
| 12:10 | Energy-Efficient 360-Degree Video Rendering on FPGA via Algorithm-Architecture Co-Design |
| Qiuyue Sun (University of Rochester); Amir Taherin(University of Rochester); Yawo Siatitse(University of Rochester); Yuhao Zhu (University of Rochester) | |
| 12:15 | Real-Time Spatial 3D Audio Synthesis on FPGAs for Blind Sailing |
| Anish Singhani(Olin College of Engineering); Alexander Morrow(Olin College of Engineering) | |
| 12:20 | Lunch |
| 13:45 | Session: Deep Learning I (Chair: Bita Rouhani, Microsoft) |
| 13:45 | When massive GPU parallelism ain’t enough: A Novel Hardware Architecture of 2D-LSTM Neural Network |
| Vladimir Rybalkin(University of Kaiserslautern); Norbert Wehn(University of Kaiserslautern) | |
| 14:10 | Light-OPU: An FPGA-based Overlay Processor for Lightweight Convolutional Neural Networks |
| Yunxuan Yu(Rednova Innovations Inc); Tiandong Zhao(Rednova Innovations Inc); Kun Wang(Rednova Innovations Inc); Lei He(ECE department, UCLA) | |
| 14:35 | End-to-End Optimization of Deep Learning Applications |
| Atefeh Sohrabizadeh(University of California Los Angeles); Jie Wang(UCLA); Jason Cong(UCLA) | |
| 14:40 | Poster Session II (Chair: Mike Hutton, Google) |
| 15:50 | Session: FPGA Architecture (Chair: Satwant Singh, Lattice Semiconductor Corp) |
| 15:50 | Architectural Enhancements in Intel Agilex FPGAs |
| Jeff Chromczak(Intel); Mark Wheeler(Intel); Charles Chiasson(Intel); Dana How(Intel); Martin Langhammer(Intel); Tim Vanderhoek(Intel); Grace Zgheib(Intel Corporation); Ilya Ganusov(Intel) | |
| 16:15 | Straight to the Point: Intra- and Inter-Cluster LUT Connections to Mitigate the Delay of Programmable Routing |
| Stefan Nikolic(EPFL); Grace Zgheib(Intel Corporation); Paolo Ienne(EPFL) | |
| 16:40 | LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations |
| Seyedramin Rasoulinezhad(University of Sydney); Siddhartha -(University of Sydney); Hao Zhou(Fudan University); Lingli Wang(Fudan University); David Boland(University of Sydney); Philip H.W. Leong(University of Sydney) | |
| 17:05 | Steering Committee Meeting |
| 18:30 | Dinner |
| Panel (Chair: Raymond Nijssen, Achronix) | |
| FPGAs will never be the same again: How the newest FPGA architectures are totally disrupting the entire FPGA ecosystem as we know | |
| Tuesday February 25 | |
| 8:30 | Keynote II: Xilinx’s Vitis Unified Software Platform (Chair: George Constantinides, Imperial College London) |
| Vinod Kathail (Xilinx) | |
| 9:00 | Session: High-Level Abstractions and Tools II (Chair: Ilya Ganusov, Intel) |
| 9:00 | StateMover: Combining Simulation and Hardware Execution for Efficient FPGA Debugging |
| Sameh Attia(University of Toronto); Vaughn Betz(University of Toronto) | |
| 9:25 | Buffer Placement and Sizing for High-Performance Dataflow Circuits |
| Lana Josipovic(École polytechnique fédérale de Lausanne); Shabnam Sheikhha(EPFL); Andrea Guerrieri(EPFL); Paolo Ienne(EPFL); Jordi Cortadella(Universitat Politecnica de Catalunya) | |
| 9:50 | Closing Leaks: Routing Against Crosstalk Side-Channel Attacks |
| Zeinab Seifoori(Department of Computer Engineering, Sharif University of Technology (SUT)); Seyedeh Sharareh Mirzargar(EPFL); Mirjana Stojilovic(EPFL) | |
| 9:55 | Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs |
| Ognjen Glamocanin(École Polytechnique Fédérale de Lausanne (EPFL)); Louis Coulon(École Polytechnique Fédérale de Lausanne (EPFL)); Francesco Regazzoni(ALaRI); Mirjana Stojilovic(EPFL) | |
| 10:00 | Poster Session III (Chair: Kia Bazargan, University of Minnesota) |
| 11:10 | Session: Applications II (Chair: Grace Zgheib, Intel) |
| 11:10 | Dependency-Driven Trace-Based Network-on-Chip Emulation on FPGAs |
| Thiem V. Chu(Japan Advanced Institute of Science and Technology); Kenji Kise(Tokyo Institute of Technology); Kiyofumi Tanaka(Japan Advanced Institute of Science and Technology) | |
| 11:35 | FPGA-Accelerated Samplesort For Large Data Sets |
| Han Chen(Stony Brook University); Sergey Madaminov(Stony Brook University); Michael Ferdman(Stony Brook University); Peter Milder(Stony Brook University) | |
| 12:00 | BiS-KM: Enabling Any-Precision K-Means on FPGAs |
| Zhenhao He(ETH Zurich); Zeke Wang(ETH Zurich); Gustavo Alonso(ETH Zurich) | |
| 12:25 | Flexible Communication Avoiding Matrix Multiplication on FPGA with High-Level Synthesis |
| Johannes de Fine Licht(ETH Zurich); Grzegorz Kwasniewski(ETH Zurich); Torsten Hoefler(ETH Zurich) | |
| 12:50 | Lunch |
| 14:10 | Session: Deep Learning II (Chair: Lita Yang, Microsoft) |
| 14:10 | Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms |
| Hanqing Zeng(University of Southern California); Viktor Prasanna(University of Southern California) | |
| 14:35 | Reuse Kernels or Activations? A Flexible Dataflow for Low-latency Spectral CNN Acceleration |
| Yue Niu(University of Southern California); Rajgopal Kannan(USC); Ajitesh Srivastava(University of Southern California); Viktor K Prasanna(University of Southern California) | |
| 15:00 | Coffee Break |
| 16:00 | Session: High-Level Synthesis and Tools (Chair: Peter Cheung, Imperial College London) |
| 16:00 | Finding and Understanding Bugs in FPGA Synthesis Tools |
| Yann Herklotz(Imperial College London); John Wickerson(Imperial College London) | |
| 16:25 | Combining Dynamic & Static Scheduling in High-level Synthesis |
| Jianyi Cheng(Imperial College London); Lana Josipovic(École polytechnique fédérale de Lausanne); George Constantinides(Imperial College London); Paolo Ienne(EPFL); John Wickerson(Imperial College London) | |
| 16:50 | Boyi: A Systematic Framework for Automatically Deciding the Best Execution Model for OpenCL Applications on FPGAs |
| Jiantong Jiang(Northeastern University); Xue Liu(Northeastern University); Juan Gómez-Luna(ETH Zurich); Nan Guan(The Hong Kong Polytechnic University); Qingxu Deng(Northeastern University); Wei Zhang(Hong Kong University of Science and Technology); Onur Mutlu(ETH Zurich and Carnegie Mellon University); Zeke Wang(ETH Zurich) | |
| 17:15 | Conference closing- Best Paper Award |
| Title | Authors |
|---|---|
| HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration | Jiajie Li(Tsinghua University); Yuze Chi(University of California, Los Angeles); Jason Cong(UCLA) |
| Fingerprinting Cloud FPGA Infrastructures | Shanquan Tian(Yale University); Wenjie Xiong(Yale University); Ilias Giechaskiel(University of Oxford); Kasper Rasmussen(University of Oxford); Jakub Szefer(Yale University) |
| Programming Abstractions for Configurable Hardware: Survey and Research Directions | Samuel Dewan (Carleton University); Paulo Garcia (Carleton University) |
| Pipeline-aware Logic Deduplication in High-Level Synthesis for Post-Quantum Cryptography Algorithms | Changsu Kim(POSTECH); Yongwoo Lee(Yonsei University); Shinnung Jeong(Yonsei University); Wen Wang(Yale University); Hanjun Kim(Yonsei University); Jakub Szefer(Yale University) |
| Advanced Dataflow Programming using Actor Machines for High-Level Synthesis | Endri Bezati(EPFL VLSC); Mahyar Emami(EPFL VLSC); James Larus(EPFL VLSC) |
| Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency | Licheng Guo(UCLA); Jason Lau(UCLA); Jie Wang(UCLA); Cody Hao Yu(University of California, Los Angeles; Falcon Computing Solutions, Inc); Yuze Chi(University of California, Los Angeles); Zhe Chen(Computer Science Department, UCLA); Zhiru Zhang(Cornell University); Jason Cong(UCLA) |
| Productive Hardware Designs using Hybrid HLS-RTL Development | Blaise Tine(Georgia Tech); Lee Seyong(Oak Ridge National Laboratory); Jeff Vetter(Oak Ridge National Laboratory); Kim Hyesoon(Georgia Tech) |
| Unleashing The Power of FPGAs as Programmable Switches | Thomas Luinaud(Polytechnique Montréal, Canada); Thibaut Stimpfling(Polytechnique Montréal); Jeferson Santiago da Silva(Polytechnique Montreal); Yvon Savaria(Polytechnique Montreal); J.M. Pierre Langlois(Polytechnique Montreal) |
| Building Reconfigurable Shared Accelerators through Early-stage Automated Identification of Similar Hardware Implementations with Abstract Syntax Trees | Parnian Mokri(Student); Maziar Amiraski(Tufts University); Yuelin Liu(Tufts university); Mark Hempstead(Tufts University) |
| Hardware Description Beyond Register-Transfer Level Languages | Oron Port(Technion - Israel Institute of Technology); Yoav Etsion(Technion - Israel Institute of Technology) |
| MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows | Pingakshya Goswami(University of Texas at Dallas); Dinesh Bhatia(University of Texas at Dallas); Masoud Shahshahani(University of Texas at Dallas) |
| A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow | Prashanth Mohan(Carnegie Mellon University); Ahmet Oguz Atli(Carnegie Mellon Univeristy); Onur O Kibar(Carnegie Mellon University); Ken Mai(Carnegie Mellon Univeristy) |
| ConvCloud: An Adaptive Convolutional Neural Network Accelerator on Cloud FPGAs | Yang Yang(University of Science and Technology of China); Chao Wang(University of Science and Technology of China); Lei Gong(University of Science and Technology of China); Xuehai Zhou(University of Science and Technology of China) |
| Scalable FPGA Median Filtering using Multiple Efficient Passes | Oscar Rahnama(University of Oxford); Tommaso Cavallari(Oxford Research Group, FiveAI); Philip Torr(University of Oxford); Stuart Golodetz(FiveAI) |
| FeCaffe: FPGA-enabled Caffe with OpenCL for Deep Learning Training and Inference on Intel Stratix 10 | Ke He(Intel IoTG Vision Market Channel PRC); Bo Liu(Intel Flex Services); Yu Zhang(Intel IoTG Vision Market Channel PRC); Andrew Ling(Intel PSG); Dian Gu(IoTG Vision Market Channel PRC) |
| Title | Authors |
|---|---|
| Real-Time Spatial 3D Audio Synthesis on FPGAs for Blind Sailing | Anish Singhani(Olin College of Engineering); Alexander Morrow(Olin College of Engineering) |
| Energy-Efficient 360-Degree Video Rendering on FPGA via Algorithm-Architecture Co-Design | Qiuyue Sun (University of Rochester); Amir Taherin(University of Rochester); Yawo Siatitse(University of Rochester); Yuhao Zhu (University of Rochester) |
| End-to-End Optimization of Deep Learning Applications | Atefeh Sohrabizadeh(University of California Los Angeles); Jie Wang(UCLA); Jason Cong(UCLA) |
| DOMIS: Dual-Bank Optimal Micro-Architecture for Iterative Stencils | Juan Escobedo(University of Central Florida); Mingjie Lin(University of Central Florida) |
| Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement | Junzhong Shen, Mei Wen, Minjin Tang, Xiaolei Zhao and Chunyuan Zhang |
| Best of Both Worlds: AutoML Codesign of a CNN and its FPGA Accelerator | Mohamed Abdelfattah(Samsung AI Center); Lukasz Dudziak(Samsung AI Center); Thomas Chau(Samsung AI Center); Royson Lee(Samsung AI Center); Nicholas Lane(University of Oxford); Hyeji Kim(Samsung AI Center) |
| Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion | Ayan Palchaudhuri(Indian Institute of Technology Kharagpur); Sandeep Sharma(Indian Institute of Technology Kharagpur); Anindya Sundar Dhar(Indian Institute of Technology Kharagpur) |
| INCAME : INterruptable CNN Accelerator for Multi-robot Exploration | Jincheng Yu(Tsinghua University, Beijing, China); Zhilin Xu(Tsinghua University, Beijing, China); Shulin Zeng(Tsinghua University, Beijing, China); Chao Yu(Tsinghua University, Beijing, China); Jiantao Qiu(Tsinghua University, Beijing, China); Chaoyang Shen(Tsinghua University, Beijing, China); Yuanfan Xu(Tsinghua University, Beijing, China); Guohao Dai(Tsinghua University, Beijing, China); Yu Wang(Tsinghua University, Beijing, China); Huazhong Yang(Tsinghua University, Beijing, China) |
| LPAC: A Low-Precision Accelerator for CNN on FPGAs | Tianyu Zhang(Xilinx Inc.); Tiantian Han(Xilinx Inc.); Lu Tian(Xilinx Inc.); Yi Li(Xilinx Inc.); Xijie Jia(Xilinx Inc); Guangdong Liu(Xilinx Inc.); Pingbo An(Xilinx Inc.); Yingran Tan(Xilinx Inc.); Lingzhi Sui(Xilinx Inc.); Shaoxia Fang(Xilinx Inc.); Dongliang Xie(Xilinx Inc.); Michaela Blott(Xilinx); Yi Shan(Xilinx Inc.) |
| Enable Efficient and Flexible FPGA Virtualization for Deep Learning in the Cloud | Shulin Zeng(Tsinghua university); Guohao Dai(Tsinghua University; VirtAI Tech); Kai Zhong(Tsinghua University); Hanbo Sun(Tsinghua University); Guangjun Ge(Tsinghua University); Kaiyuan Guo(Tsinghua University); Huazhong Yang(Tsinghua University) |
| Evaluation of Optimized CNNs on a Spectrum of FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach | Michaela Blott(Xilinx); Johannes Kah(Xilinx); Giulio Gambardella(Xilinx); Yaman Umuroglu(Xilinx); Lisa Halder(Xilinx); Nicholas Fraser(Xilinx); Linda Doyle(TCD); Miriam Leeser(Northeastern University) |
| CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors | Mirjana Stojilovic(EPFL); Seyedeh Sharareh Mirzargar(EPFL); Andrea Guerrieri(EPFL) |
| Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL | Adel Ejjeh(University of Illinois at Urbana Champaign); Vikram Adve(University of Illinois at Urbana-Champaign); Rob Rutenbar(University of Pittsburgh) |
| CANSEE: Customized Accelerator for Neural Signal Enhancement and Extraction in Real Time | Zhe Chen(Computer Science Department, UCLA); Garrett Blair(Department of Psychology, UCLA); Riley Seow(Stanford University); Hugh Blair(Department of Psychology, UCLA); Jason Cong(UCLA) |
| Low Precision Floating Point Arithmetic for High Performance FPGA-based CNN Acceleration | Chen Wu(Rednova Innovations Inc); Mingyu Wang(Rednova Innovations Inc); Xinyuan Chu(Rednova Innovations Inc); Kun Wang(Rednova Innovations Inc); Lei He(University of California, Los Angeles) |
| Maximizing CNN Throughput on FPGA Clusters | Ruihao Li(Shandong University); Ke Liu(Shandong University); Mengying Zhao(Shandong University); Zhaoyan Shen(Shandong University); Xiaojun Cai(Shandong University); Zhiping Jia(Shandong University) |
| R2CNN: Recurrent Residual Convolutional Neural Network on FPGA | Hiroki Nakahara(Tokyo Institute of Technology); Que Zhiqiang(Imperial College London); Akira Jinguji(Tokyo Institute of Technology); Wayne Luk(Imperial College) |
| Synthesis-Free, Flexible and Fast Hardware Library for Biophysically Plausible Neurosimulations | Rene Miedema(Erasmus MC); Georgios Smaragdos(Erasmus Medical Center); Mario Negrello(Erasmus Medical Center); Matthias Möller(Delft University of Technology); Zaid Al-Ars(Delft University of Technology); Christos Strydis(Erasmus Medical Center) |
| HPIPE: Heterogeneous Layer-Pipelined and Sparse-Aware CNN Inference for FPGAs | Mathew Hall(University of Toronto); Vaughn Betz(University of Toronto) |
| FTDL: An FPGA-tailored Architecture for Deep Learning Applications | Runbin Shi(The University of Hong Kong); Yuhao Ding(The University of Hong Kong); Xuechao Wei(Peking University); Hang Liu(Stevens Institute of Technology); Hayden So(University of Hong Kong); Caiwen Ding(University of Connecticut) |
| Title | Authors |
|---|---|
| Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs | Ognjen Glamocanin(École Polytechnique Fédérale de Lausanne (EPFL)); Louis Coulon(École Polytechnique Fédérale de Lausanne (EPFL)); Francesco Regazzoni(ALaRI); Mirjana Stojilovic(EPFL) |
| Closing Leaks: Routing Against Crosstalk Side-Channel Attacks | Zeinab Seifoori(Department of Computer Engineering, Sharif University of Technology (SUT)); Seyedeh Sharareh Mirzargar(EPFL); Mirjana Stojilovic(EPFL) |
| Cash: A Single-Source Hardware-Software Codesign Framework for Rapid Prototyping | Blaise Tine(Georgia Tech); Elsabbagh Fares(GeorgiaTech); Jeff Vetter(Oak Ridge National Laboratory); kim hyesoon(Georgia Tech) |
| Performance Evaluation and Power Analysis of Teraflop-scale Fluid Simulation with Stratix 10 FPGA | Atsushi Koshiba(RIKEN Center for Computational Science); Kouki Watanabe(RIKEN Center for Computational Science, Tohoku University); Takaaki Miyajima(Japan Aerospace Exploration Agency); Kentaro Sano(RIKEN Center for Computational Science) |
| On the Exploration of Connection-based Partitioning for Parallel FPGA Routing | Yun Zhou(Ghent University); Dries Vercruyce(Ghent University); Dirk Stroobandt(Ghent University) |
| High Density INT8 Pipelined Systolic Array | Martin Langhammer(Intel); Sergey Gribok(Intel); Gregg Baeckler(Intel) |
| Reactive Signal Obfuscation with Time-Fracturing to Counter Information Leakage in FPGAs | Stephen Williams(University of Central Florida); Mingjie Lin(University of Central Florida) |
| Cycle-Free FPGA Routing Graphs | Ang Li(Princeton University); David Wentzlaff(Princeton University) |
| An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops | Rupesh Shelar(Synopsys, Inc.) |
| QTAccel: A Generic FPGA Architecture for Q-Table based Reinforcement Learning Accelerators | Rachit Rajat(University of Southern California); Yuan Meng(University of Southern California); Sanmukh Kuppannagari(University of Southern California); Ajitesh Srivastava(University of Southern California); Rajgopal Kannan(USC); Viktor Prasanna(University of Southern California) |
| The Case for Hard Matrix Multiplier Blocks in an FPGA | Aman Arora(The University of Texas at Austin); Zhigang Wei(The University of Texas at Austin); Lizy John(The University of Texas at Austin) |
| Performance Portable FPGA Design | Nils Voss(Imperial College London); Tobias Becker(Maxeler Technologies); Simon Tilbury(Maxeler Technologies); Anna Maria Nestorov(Politecnico di Milano, Dipartimento di Elettronica); Enrico Reggiani(Politecnico di Milano, Dipartimento di Elettronica); Oskar Mencer(Maxeler Technologies); Georgi Gaydadjiev(Maxeler / Imperial College); Wayne Luk(Imperial College) |
| Accuracy-Aware Memory Allocation to Mitigate BRAM Errors for Voltage Underscaling on FPGA Overlay Accelerators | Tanvir Ahmed(Preferred Networks, Inc.); Johannes Maximilian Kühn(Preferred Networks, Inc.) |
| Near-memory Acceleration for Scalable Phylogenetic Inference | Nikolaos Alachiotis(Technical University of Crete, Chania, Greece); Panagiotis Skrimponis(NYU Tandon School of Engineering, Brooklyn, NY, USA); Emmanouil Pissadakis(Technical University of Crete, Chania, Greece); Dionisios Pnevmatikatos(National Technical University of Athens, Athens, Greece) |
| FPTLOPT: An Automatic Transistor-Level Optimization Tool for GRM FPGA | Yufan Zhang(Fudan University); Zhengjie Li(Fudan University); Jian Wang(Fudan University); Jinmei Lai(Fudan University) |
| INTB: A New FPGA Interconnect Model for Architecture Exploration | Chengyu Hu(Fudan University); Peng Lu(Fudan University); Wei Liu(Fudan University); Liran Hu(Fudan University); Jian Wang(Fudan University); Jinmei Lai(Fudan University) |
| V-LSTM: An Efficient LSTM Accelerator using Fixed Nonzero-Ratio Viterbi-Based Pruning | Taesu Kim(Pohang University of Science and Technology); Daehyun Ahn(POSTECH); Jae-Joon Kim(Pohang University of Science and Techology) |
| DBHI: a tool for decoupled functional hardware-software co-design on SoCs | Unai Martinez-Corral(University of the Basque Country); Guillermo Callaghan(The University of Manchester); Konstantinos Iordanou(The University of Manchester); Cosmin Gorgovan(The University of Manchester); Koldo Basterretxea(University of the Basque Country); Mikel Lujan(The University of Manchester) |