{"id":346,"date":"2021-01-09T03:39:57","date_gmt":"2021-01-09T03:39:57","guid":{"rendered":"https:\/\/isfpga.org\/?page_id=346"},"modified":"2021-02-27T21:29:01","modified_gmt":"2021-02-27T21:29:01","slug":"workshops-tutorials","status":"publish","type":"page","link":"https:\/\/wp.isfpga.org\/workshops-tutorials\/","title":{"rendered":"Workshops & Tutorials"},"content":{"rendered":"\n


Tutorials<\/strong> and Workshops<\/h2>\n\n\n\n

All times shown in Pacific Standard Time (UTC-8)<\/strong><\/p>\n\n\n\n

Please use the Registration page to register for the workshops. All workshops will send emails to registered participants.
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Enhancing and Simplifying HLS with Xilinx Vitis Open Source and Silexica Tools<\/strong><\/strong><\/h3>\n\n\n\n

Time: February 28, 8:00 AM – 10:00 AM PST<\/h4>\n\n\n\n

Organizers: Liam Fitzpatrick (Silexica), Luis G. Murillo (Silexica), Alexandre Isoard (Xilinx), Lin-Ya Yu (Xilinx), DJ Wang (Xilinx), Frederic Rivoallon (Xilinx)
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In line with Xilinx\u2019s Open Source strategy, the Clang components of Vitis HLS are being open sourced. This gives the community the possibility to extend, customize and even further optimize the HLS compilation process. This new open source initiative also comes with the radically new \u201cinjection use model\u201d for Vitis HLS that makes it possible to inject custom third-party code transformations, or even use a completely custom Clang compiler front-end. In close collaboration with Xilinx, Silexica has created a plugin, namely the SLX Plugin, that extends Vitis HLS 2020.2 code transformations, leveraging the new injection use model. The SLX Plugin is an HLS compiler add-on that helps improve Vitis HLS latency and throughput results by providing a new Loop Interchange directive. This is the first of many planned HLS optimization directives from Silexica. The plugin can be used as a pure standalone addition to Vitis HLS, or in combination with Silexica\u2019s SLX FPGA tool to benefit from its deep code analysis, automatic design exploration, and optimal directive identification and tuning capabilities. This tutorial provides a deep dive into Xilinx\u2019 open source Clang, the Vitis HLS injection use model, and how Silexica\u2019s SLX Plugin and SLX FPGA make use of the model to help FPGA developers achieve better results for a set of common design styles.<\/p>\n\n\n\n

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AI Optimized Intel\u00ae<\/sup> Stratix\u00ae<\/sup> 10 NX FPGA<\/strong><\/strong><\/h3>\n\n\n\n

Time: February 28, 8:00 AM – 10:00 AM PST<\/h4>\n\n\n\n

Organizer: Eriko Nurvitadhi (Intel)
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The Intel\u00ae Stratix\u00ae 10 NX FPGA is Intel’s first AI-optimized FPGA. It introduces a new type of AI-optimized tensor arithmetic block called the AI Tensor Block and is designed for high-bandwidth, low-latency, artificial intelligence (AI) applications. The Intel\u00ae Stratix\u00ae 10 NX FPGA delivers accelerated AI compute solutions with up to 143 INT8 TOPS at ~1 TOPS\/W, in package 3D stacked HBM2 high-bandwidth DRAM, and up to 57.8G PAM4 transceivers. In this tutorial, we will first provide an overview of the Intel Stratix 10 NX FPGA followed by an application evaluation and comparison against GPUs. Using an approach such as the soft AI processor overlay we developed in our recently published research, we will show how the Intel Stratix 10 NX FPGA can be programmed purely in software to deliver excellent performance in real-time AI workloads.<\/p>\n\n\n\n

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A Low-Cost Teaching and Research Platform Based on Xilinx RFSoC Technology and the PYNQ Framework<\/strong><\/strong><\/strong><\/h3>\n\n\n\n

Time: February 28, 8:00 AM – 10:00 AM PST<\/h4>\n\n\n\n

Organizer: Patrick Lysaght (Xilinx), Robert W. Stewart (Strathclyde)<\/p>\n\n\n\n

The Xilinx Zynq\u00ae UltraScale+\u2122 RFSoC architecture integrates ZU+ MPSoCs with state-of-the-art, analog-to-digital (ADC) and digital-to-analog (DAC) data converters. The combination of banks of high-precision data converters, capable of processing multi giga samples of data per second, along with FPGA fabric and ARM processors creates a uniquely powerful family architecture.  RFSoC technology re-defines what is possible in applications such as software defined radio (SDR) and advanced instrumentation. <\/p>\n\n\n\n

This tutorial introduces a new low-cost teaching and research platform for RFSoC, designed especially for academia. The platform exploits the PYNQ open-source framework to provide a highly intuitive user system interface incorporating Linux, Python and Jupyter notebooks. It also comes with a suite of open-source teaching resources including videos, notebooks and design examples.<\/p>\n\n\n\n

We will demonstrate the benefits of integrating direct RF sampling data converters by introducing  a novel, open-source spectrum analyzer built using the new board. This RFSoC design exploits advanced signal processing techniques, including higher-order Nyquist zones, to demonstrate performance that has only previously been achieved on very high-end instrumentation. Using the spectrum analyzer example, we will also demonstrate new approaches to the rapid prototyping of graphical user interfaces for research demonstrators.<\/p>\n\n\n\n

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Hands-On Tutorial: Introduction to oneAPI with Intel\u00ae<\/sup> FPGAs<\/strong><\/strong><\/strong><\/h3>\n\n\n\n

Time: February 28, 10:15 AM – 12:15 PM PST<\/h4>\n\n\n\n

Organizer: Susannah Martin (Intel)<\/p>\n\n\n\n

DPC++ is a programming language based on SYCL that can be used to target algorithms to an FPGA or other devices in a heterogeneous compute environment with an x86 host. This tutorial will teach you how to use the oneAPI software model to create Data Parallel C++ programs to target supported FPGA acceleration cards. You will learn how your source code is interpreted by the compiler to build a custom hardware datapath. You will learn the 3-step flow for development: (1) emulation, (2) using the static optimization report to fine tune your implementation, and (3) compiling a bitstream for the FPGA. You will be introduced to optimization concepts including pipelining loop iterations and architecting kernel memory, which are important when targeting FPGAs. In the second hour of the tutorial, you will practice the multi-step development flow, and progress through code emulation and several stages of optimization with sample code implementing the Hough Transform. The lab portion will use JupyterLab* on  the Intel\u00ae<\/sup> DevCloud for oneAPI \u2013 which requires only a web browser to access an environment to work with the latest toolset.<\/p>\n\n\n\n

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Neural Network Accelerator Co-Design with FINN<\/strong><\/strong><\/strong><\/strong><\/h3>\n\n\n\n

Time: February 28, 10:30 AM – 1:30 PM PST<\/h4>\n\n\n\n

Organizer: Michaela Blott (Xilinx), Yaman Umuroglu (Xilinx), Zaid Al-Ars (TU Delft)<\/p>\n\n\n\n

Extra registration step required. Please register with the conference and then at http:\/\/bit.ly\/registration-finn-tutorial-fpga21<\/a>.<\/p>\n\n\n\n

Mixing machine learning into high-throughput, low-latency edge applications needs co-designed solutions to meet the performance requirements. Quantized Neural Networks (QNNs) combined with custom FPGA dataflow implementations offer a good balance of performance and flexibility, but building such implementations by hand is difficult and time-consuming. In this tutorial, we will introduce FINN, an open-source experimental framework by Xilinx Research Labs to help the broader community explore QNN inference on FPGAs. Providing a full-stack solution from quantization-aware training to bitfile, FINN generates high-performance dataflow-style FPGA architectures customized for each network. Participants will be introduced to efficient inference with QNNs and streaming dataflow architectures, the components of the project\u2019s open-source ecosystem, and gain hands-on experience training a quantized neural network with Brevitas and deploying it with FINN.<\/p>\n\n\n\n

More information available at the FINN tutorial website.<\/a><\/p>\n\n\n\n

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Intel\u00ae<\/sup> FPGA<\/strong><\/strong><\/strong> Devcloud<\/h3>\n\n\n\n

Time: February 28, 12:30 PM – 2:30 PM PST<\/h4>\n\n\n\n

Organizer: Lawrence Landis (Intel)<\/p>\n\n\n\n

Gain hands-on experience using Intel\u00ae<\/sup> FPGA development tools and kits\/accelerator cards in a remote environment. The first half of the course will focus on how to teach undergraduate level courses using Verilog\/Schematics\/Prebuilt IP and accessing Terasic\u2019s DE10-Lite kit in a remote environment. Topics covered are network setup, installation, compilation and download. The second half of the course will focus on graduate level heterogeneous computing teaching and research on the Intel\u00ae FPGA Devcloud. The Intel\u00ae FPGA Devcloud has the latest configurations of Quartus (RTL), OpenCL, OneAPI and Openvino workload compilation in a XEON+ Arria 10\/Stratix 10 FPGA development environment available free to the academic community.<\/p>\n","protected":false},"excerpt":{"rendered":"

Tutorials and Workshops All times shown in Pacific Standard Time (UTC-8) Please use the Registration page to register for the workshops. All workshops will send emails to registered participants. Enhancing and Simplifying HLS with Xilinx Vitis Open Source and Silexica Tools Time: February 28, 8:00 AM – 10:00 AM PST Organizers: Liam Fitzpatrick (Silexica), Luis […]<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":[],"_links":{"self":[{"href":"https:\/\/wp.isfpga.org\/wp-json\/wp\/v2\/pages\/346"}],"collection":[{"href":"https:\/\/wp.isfpga.org\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/wp.isfpga.org\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/wp.isfpga.org\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/wp.isfpga.org\/wp-json\/wp\/v2\/comments?post=346"}],"version-history":[{"count":5,"href":"https:\/\/wp.isfpga.org\/wp-json\/wp\/v2\/pages\/346\/revisions"}],"predecessor-version":[{"id":507,"href":"https:\/\/wp.isfpga.org\/wp-json\/wp\/v2\/pages\/346\/revisions\/507"}],"wp:attachment":[{"href":"https:\/\/wp.isfpga.org\/wp-json\/wp\/v2\/media?parent=346"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}