FPGA 2015

Program with Slides

Sunday February 22

Designer’s Day

This year, FPGA’15 program contains a new full-day event called Designer’s Day. This new track would provide tutorials and design experiences on known-interesting topics for FPGAs describing effective design techniques, design flows, methods, and new tool features. The goal of the event is to bring FPGA users, designers, experts, consultants, and researchers together to share design experiences and learn new design solutions.

9:00am-9:05am Introduction (Ferrante Room, Monterey Conf. Center) [slides]

Stephen Neuendorffer, Xilinx, Inc.

9:05am-10:25am Session 1 (Ferrante Room, Monterey Conf. Center)

Chair: Satwant Singh, Lattice Semiconductor Corp.

(60 min) Physical Design Space Exploration
Ephrem Wu, Inkeun Cho (Xilinx, Inc.)

(Pushing the boundaries of high speed FPGA design)

(20 min) Using Source-Level Transformations to Improve High-Level Synthesis Debug and Validation on FPGAs

Joshua Monson, Brad Hutchings (Brigham Young University) (Improving in-system debug for HLS accelerators)

10:25am-10:40am Break

10:40am-12:20pm Session 2 (Ferrante Room, Monterey Conf. Center)

Chair: Zhiru Zhang, Cornell University

(60 min) High Level Design Methods for Floating Point FPGAs Deshanand P. Singh, Bogdan Pasca, Tomasz S. Czajkowski (Altera, Inc.) (New Floating Point support in Altera FPGAs)

(20 min) Software-Driven Hardware Development

Myron King, Jamey Hicks, John Ankcorn (Quanta Research Cambridge) (Design tradeoffs in Processor/Accelerator Communication)

(20 min) InTime: A Machine Learning Approach for Efficient Selection of FPGA CAD Tool Parameters

Nachiket Kapre (Nanyang Technological University), Harnhua Ng, Kirvy Teo, Jaco Naude (Plunify, Inc.) (Automatically tune EDA tools to meet timing more quickly)

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12:20pm-1:50pm

Lunch (Marriott Hotel Ferrantes Bayview Room – 10th floor)

1:50pm-3:30 pm

Session 3 (Ferrante Room, Monterey Conf. Center)

 

Chair: Patrick Lysaght, Xilinx, Inc.

(60 min) Unlocking FPGAs Using High-Level Synthesis Compiler Technologies Fernando Martinez Vallina, Henry Styles (Xilinx, Inc.)

(Building complete FPGA systems with HLS)

(20 min) Enhancing Hardware Design Flows within MyHDL Keerthan Jaic, Melissa C. Smith (Clemson University) (Generating FPGA designs using Python Libraries)

(20 min) Rapid Prototyping of Wireless Physical Layer Modules Using Flexible Software/Hardware Design Flow

James Chacko, Cem Sahin, Douglas Pfiel, Nagarajan Kandasamy, Kapil Dandekar (Drexel University) (Practical techniques for designing and implementing Software Designed Radio (SDR) systems)

3:30 pm-3:45 pm Break

3:45pm-5:00pm Keynote Speech (Ferrante Room, Monterey Conf. Center)

Chen Cheng, CEO, BEEcube, Inc.

The BEEcube Story—Lessons Learned from Running a FPGA Startup for the Past 7 Years

Abstract:

After running BEEcube Inc for the past 7 years, I learned many lessons the hard way as an entrepreneur fresh out of engineer school. Behind the glory of being the #9 fastest growing private company in Silicon Valley in 2013, there were many untold stories about our FPGA technology based startup company. A startup company is where dreams start by smart people, and also where harsh reality squashes them. This is not one of those “unicorn” billion-dollar-valuation-in-18-month stories, but rather a bootstrap startup manage to find it’s own pot of gold under the rainbow.

Presenter Bio:

Dr. Chen Chang is the Chief Executive Officer at BEEcube Inc. Previously he served as Chief Technology Officer at BEEcube where he led the development of the BEE3 product. Dr. Chang was the Chief Architect of the Berkeley Emulation Engine (BEE) project at the University of California in Berkeley, leading the design and implementation of three generations of FPGA-based emulation and computing systems, as well as unified FPGA/ASIC design environment using high-level descriptions from Mathworks Simulink environment. His research interests include large-scale FPGA-based real- time computer systems; digital systems design automation and hardware emulation; and wideband antenna array signal processing systems. Dr. Chang is a young entrepreneur who co-founded BEEcube in 2006 with professors from the University of California, Berkeley. He also participates actively in assisting many of the world's universities in FPGA-related research projects and academic exchanges. Dr. Chang holds B.Sc., M.Sc. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley.

7:00pm Conference Reception (Marriott Hotel Ferrantes Bayview Room)

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Monday February 23

8:00am Continental Breakfast & Registration (Steinbeck Lobby/Conf. Center)

8:40am Opening Remarks (Steinbeck Forum/Conf. Center)

Deming Chen and George A. Constantinides

9:00am Session 1: Computer-aided Design (Steinbeck Forum)

Chair: Herman Schmit, Altera, Inc.

Long paper: 25 minutes. Short paper: 5 minutes

Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs (Best

Paper Candidate)

Evan Wegley, Qinhai Zhang (Lattice Semiconductor Corp.)

Fine-Grained Interconnect Synthesis

Alex Rodionov (University of Toronto), David Biancolin (University of California, Berkeley), Jonathan Rose (University of Toronto)

Delay-Bounded Routing for Shadow Registers

Eddie Hung, Joshua M. Levine, Edward Stott, George A. Constantinides, Wayne Luk (Imperial College London)

RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs (short) Travis Haroldsen, Brent Nelson, Brad Hutchings (Brigham Young University)

Technology Mapping into General Programmable Cells (short)

Alan Mishchenko, Robert Brayton (University of California, Berkeley),

Wenyi Feng, Jonathan Greene (Microsemi Corp.)

10:25am Poster Session 1 (Colton Room/Conf. Center)

12 posters (please refer to the list below)

11:25am Session 2: Configuration and Processing (Steinbeck Forum)

Chair: Steve Trimberger, Xilinx, Inc.

EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access Xinyu Niu, Wayne Luk (Imperial College London), Yu Wang (Tsinghua University)

Energy-Efficient Discrete Signal Processing with Field Programmable Analog Arrays (FPAAs) Yu Bai, Mingjie Lin (University of Central Florida)

Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware (short)

Stuart Byma, Naif Tarafdar, Talia Xu, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow (University of Toronto)

12:20pm Lunch (Marriott Hotel Ferrantes Bayview Room)

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2:00pm Session 3: Architecture 1 (Steinbeck Forum)

Chair: Jonathan Rose, University of Toronto

Take the Highway: Design for Embedded NoCs on FPGAs (Best Paper Candidate) Mohamed S. Abdelfattah, Andrew Bitar, Vaughn Betz (University of Toronto)

Enhancements in UltraScale CLB Architecture

Shant Chandrakar, Dinesh Gaitonde, Trevor Bauer (Xilinx, Inc.)

Floating-Point DSP block Architecture for FPGAs

Martin Langhammer, Bogdan Pasca (Altera European Technology Centre)

3:15pm Poster Session 2 (Colton Room)

12 posters (please refer to the list below)

4:15pm Session 4: Architecture 2: Memory Systems (Steinbeck Forum)

Chair: Carl Ebeling, Altera, Inc.

Superoptimized Memory Subsystems for Streaming Applications

Joseph G. Wingbermuehle, Ron K. Cytron, Roger D. Chamberlain (Washington University, St. Louis)

MATCHUP: Memory Abstractions for Heap Manipulating Programs

Felix Winterstein (European Space Agency), Kermin Fleming (Intel Corporation), Hsin-Jung Yang (Massachusetts Institute of Technology),

Samuel Bayliss, George Constantinides (Imperial College London)

Impact of Memory Architecture on FPGA Energy Consumption

Edin Kadric, David Lakata, André DeHon (University of Pennsylvania)

Design Space Exploration of L1 Data Caches for FPGA-Based Multiprocessor Systems (short) Eric Matthews, Nicholas C. Doyle, Lesley Shannon (Simon Fraser University)

5:35pm Break before Banquet

6:30pm Banquet & Panel (Marriott Hotel Ferrantes Bayview Room)

Panel: Building a Healthy FPGA Ecosystem

Moderator: John Lockwood, Algo-Logic Systems, Inc.

Panelists: Michael Adler (Intel), Dan Mansur (Xilinx), Derek Chiou (Microsoft), Mike Strickland (Altera), Jason Cong (University of California, Los Angeles), Allen Cantle (Nallatech)

The focus of the panel will be on how developers and vendors can bring killer applications, tools, and programmable logic devices to the market to accelerate datacenters for cloud computing. Questions to be answered by the panelists include:

1.How large can the ecosystem for programmable logic become?

2.What are you doing to help grow the programmable logic ecosystem?

3.What do you ask of others to grow the programmable logic ecosystem?

4.What is your call to action for the attendees of the FPGA’15 conference?

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Tuesday February 24

8:20am Continental Breakfast & Registration (Steinbeck Lobby)

9:00am Session 5: Processors and Accelerators (Steinbeck Forum)

Chair: Zhiru Zhang, Cornell University

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks: An Analytical Approach based on Roofline Model (Best Paper Candidate)

Chen Zhang (Peking University), Peng Li (University of California, Los Angeles), Guangyu Sun (Peking University & University of California, Los Angeles),

Yijin Guan (Peking University), Bingjun Xiao (University of California, Los Angeles), Jason Cong (University of California, Los Angeles & Peking University)

Wavefront Skipping using BRAMs for Conditional Algorithms on Vector Processors Aaron Severance, Joe Edwards, Guy G.F. Lemieux (University of British Columbia)

On Data Forwarding in Deeply Pipelined Soft Processors

Hui Yan Cheah, Suhaib Fahmy, Nachiket Kapre (Nanyang Technological University)

10:15am Poster Session 3 (Colton Room)

11 posters (please refer to the list below)

11:15am Session 6: High-level and System-level Synthesis (Steinbeck Forum)

Chair: Brad Hutchings, Brigham Young University

Mapping-Aware Constrained Scheduling for LUT-Based FPGAs

Mingxing Tan, Steve Dai, Udit Gupta, Zhiru Zhang (Cornell University)

Resource-Aware Throughput Optimization for High-Level Synthesis Peng Li, Peng Zhang (University of California, Los Angeles),

Louis-Noël Pouchet (The Ohio State University & University of California, Los Angeles), Jason Cong (University of California, Los Angeles)

Numerical Program Optimization for High-Level Synthesis (short)

Xitong Gao, George A. Constantinides (Imperial College London)

System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System (short)

Shane Fleming, David Thomas, George Constantinides (Imperial College London), Dan Ghica (University of Birmingham)

12:15pm Lunch (Marriott Hotel Ferrantes Bayview Room)

2:00pm Session 7: Circuit Design (Steinbeck Forum)

Chair: Vaughn Betz, University of Toronto

Automatic Time-Redundancy Transformation for Fault-Tolerant Circuits

Dmitry Burlyaev, Pascal Fradet, Alain Girault (INRIA & University Grenoble Alpes)

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200 MS/s ADC Implemented in a FPGA Employing TDCs

Harald Homulle (Delft University of Technology), Francesco Regazzoni (USI - ALaRI), Edoardo Charbon (Delft University of Technology)

0.5-V Highly Power-efficient Programmable Logic Using Nonvolatile Configuration Switch in BEOL (short)

Makoto Miyamura, Toshitsugu Sakamoto, Yukihide Tsuji, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada (Low-power Electronics Association & Project (LEAP))

2:55pm

Poster Session 4 (Colton Room)

 

11 posters (please refer to the list below)

3:55

Session 8: Applications (Steinbeck Forum)

 

Chair: Kia Bazargan, University of Minnesota

Energy and Memory Efficient Mapping of Bitonic Sorting on FPGA

Ren Chen, Sruja Siriyal, Viktor Prasanna (University of Southern California, Los Angeles)

Ramethy: Reconfigurable Acceleration of Bisulfite Sequence Alignment

James Arram, Wayne Luk (Imperial College), Peiyong Jiang (The Chinese University of Hong Kong)

4:45pm Best Paper Award and Closing Remarks (Steinbeck Forum)

Deming Chen and George A. Constantinides

Posters

Poster Session 1:

An Efficient and Flexible FPGA Implementation of a Face Detection System Hichem Ben Fakih, Ahmed Elhossini, Ben Juurlink (Technical University of Berlin)

A Novel Method for Enabling FPGA Context-Switch

Alban Bourge, Olivier Muller, Frédéric Rousseau (University Grenoble Alpes)

FPGA Acceleration for Simultaneous Image Reconstruction and Segmentation Based on the Mumford-Shah Regularization

Wentai Zhang, Li Shen (Peking University), Thomas Page (University of Bremen),

Guojie Luo (Peking University), Peng Li (University of California, Los Angeles), Peter Maaß (University of Bremen), Ming Jiang (Peking University), Jason Cong (University of California, Los Angeles)

Logic Gates in the Routing Network of FPGAs

Elias Vansteenkiste, Berg Severens, Dirk Stroobandt (Ghent University)

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Real-Time Obstacle Avoidance for Mobile Robots via Stereoscopic Vision Using Reconfigurable Hardware

Martinianos Papadopoulos (University of Cyprus), Christos Ttofis (ACC Innovations Ltd), Christos Kyrkou, Theocharis Theocharides (University of Cyprus)

Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion Pierre-Emmanuel Gallardon, Gain Kim, Xifan Tang, Luca Amarù, Giovanni De Micheli (École Polytechnique Fédérale de Lausanne)

An Automated Design Framework for Floating Point Scientific Algorithms Using Field Programmable Gate Arrays (FPGAs)

Michaela E. Amoo (Howard University), Youngsoo Kim, Vance Alford, Shrikant Jadhav, Naser I. El- Bathy, Clay S. Gloster (North Carolina A&T State University)

Sequence-based In-Circuit Breakpoints for Post-Silicon Debug

Yutaka Tamiya, Yoshinori Tomita, Toshiyuki Ichiba, Kaoru Kawamura (Fujitsu Laboratories Ltd.)

Cost-Effective Memory Architecture to Achieve Flexible Configuration and Efficient Data Transmission for Coarse-Grained Reconfigurable Array

Chen Yang, Leibo Liu, Shouyi Yin, Shaojun Wei (Tsinghua University)

Exploring Efficiency of Ring Oscillator-Based Temperature Sensor Networks on FPGAs Navid Rahmanikia (Ferdowsi University of Mashhad), Amirali Amiri (Technical University of

Munich), Hamid Noori (Ferdowsi University of Mashhad), Farhad Mehdipour (Kyushu University)

Formal Verification ATPG Search Engine Emulator

Gregory Ford (IBM Microelectronic), Aswin Krishna (CWRU), Jacob A. Abraham (University of Texas, Austin), Daniel G. Saab (CWRU)

Platform-Independent Gigabit Communication for Low-Cost FPGAs

Ralf Salomon, Ralf Joost, Matthias Hinkfoth (University of Rostock)

Poster Session 2:

An FPGA-based Accelerator for the 2D Implicit FDM and Its Application to Heat Conduction Simulations

Yutaro Ishigaki, Ning Li, Yoichi Tomioka (Tokyo University of Agriculture and Technology), Akihiko Miyazaki (NTT Device Technology Laboratories),

Kitazawa Hitoshi (Tokyo University of Agriculture and Technology)

An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform

Yaoqiang Li, Pierce I-Jen Chuang, Andrew Kennings, Manoj Sachdev (University of Waterloo)

A Parallel and Scalable Multi-FPGA based Architecture for High Performance Applications Venkatasubramanian Viswanathan (Nolam Embedded Systems), Rabie Ben Atitallah (University of Valenciennes), Jean-Luc Dekeyser (University of Lille), Benjamin Nakache, Maurice Nakache (Nolam Embedded Systems)

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A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding Leibo Liu, Yingjie Chen (Tsinghua University), Dong Wang (Beijing Jiaotong University), Min Zhu, Shouyi Yin, Shaojun Wei (Tsinghua University)

FiT – An Automated Toolkit for Matching Processor Architecture to Applications

Charles Mutigwe (NxCORES Research), Johnson Kinyua (Virginia International University), Farhad Aghdasi (University of Fort Hare)

FPGA-Based BLOB Detection Using Dual-Pipelining

Naoto Nojiri, Lin Meng, Katsuhiro Yamazaki (Ritsumeikan University)

An FPGA Implementation of Multi-Stream Tracking Hardware Using 2D SIMD Array Ryota Takasu, Yoichi Tomioka (Tokyo University of Agriculture and Technology), Takashi Aoki (NTT Device Technology Laboratories),

Hitoshi Kitazawa (Tokyo University of Agriculture and Technology)

300 Thousand Gates Single Event Effect Hardened SRAM-based FPGA for Space Application Chen Lei, Zhao Yuanfu, Wen Zhiping, Zhou Jing, Li Xuewu, Zhang Yanlong, Sun Huabo (Beijing Microelectronics Technology Institute)

REPROC: A Dynamically Reconfigurable Architecture for Symmetric Cryptography Bo Wang, Leibo Liu (Tsinghua University)

Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics Xu Bai, Yukihide Tsuji, Ayuka Morioka, Makoto Miyamura, Toshi Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada (Low-power Electronics Association & Project)

A Novel Method for FPGA Test Based on Partial Reconfiguration and Sorting Algorithm Xianjian Zheng, Fan Zhang, Lei Chen, Zhiping Wen, Yuanfu Zhao, Xuewu Li

(Beijing Microelectronics Technology Institute)

A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture Junbin Wang, Leibo Liu, Jianfeng Zhu, Shouyi Yin, Shaojun Wei (Tsinghua University)

Poster Session 3:

Acceleration of Synthetic Aperture Radar (SAR) Algorithms Using Field Programmable Gate Arrays (FPGAs)

Youngsoo Kim, William Harding, Clay S. Gloster Jr. (North Carolina A&T State University), Winser Alexander (North Carolina State University)

An Embedded FPGA Operating System Optimized for Vision Computing Zhilei Chai, Jin Yu, Zhibin Wang, Jie Zhang (Jiangnan University),

Haojie Zhou (State Key Laboratory of Mathematical Engineering and Advanced Computing)

FPGA Implementation of Trained Coarse Carrier Frequency Offset Estimation and Correction for OFDM Signals

Marko Jacovic, James Chacko, Doug Pfeil, Nagarajan Kandasamy, Kapil R. Dandekar (Drexel University)

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Energy-Efficient High-Order FIR Filtering through Reconfigurable Stochastic Processing Mohammed Alawad, Mingjie Lin (University of Central Florida)

Silicon Verification Using High-Level Design Tools

Tomasz S. Czajkowski (Altera, Inc.)

A Hardware Implementation of a Unit for Geometric Algebra Operations with Parallel Memory Arrays

Gerardo Soria García, Adrian Pedroza de la Crúz, Susana Ortega Cisneros (CINVESTAV UGdl), Juan José Raygoza Panduro (CUCEI UdeG), Eduardo Bayro Corrochano (CINVESTAV UGdl)

Efficient Generation of Energy and Performance Pareto Front for FPGA Designs Sanmukh R. Kuppannagari, Viktor K. Prasanna (University of Southern California)

A Novel Coefficient Address Generation Algorithm for Split-Radix FFT

Zhuo Qian, Martin Margala (University of Massachusetts Lowell)

RapidPath: Accelerating Constrained Shortest Path Finding in Graphs on FPGA

Chao Wang, Xi Li, Qi Guo, Xuehai Zhou (University of Science and Technology of China)

High Level Programming of Document Classification Systems for Heterogeneous Environments using OpenCL

Nasibeh Nasiri, Oren Segal, Martin Margala (University of Massachusetts Lowell), Wim Vanderbauwhede (University of Glasgow), Sai Rahul Chalamalasetti (HP Servers)

Low-Resource Bluespec Design of a Modular Acquisition and Stimulation System for Neuroscience Paulo Matias, Rafael T. Guariento, Lirio O. B. de Almeida, Jan F. W. Slaets (University of São Paulo)

Poster Session 4:

Bridging Architecture and Programming for Throughput-Oriented Vision Processing Amir Momeni, Hamed Tabkhi, Gunar Schirner, David Kaeli (Northeastern University)

An Automatic Design Flow for Hybrid Parallel Computing on MPSoCs

Hongyuan Ding, Miaoqing Huang (University of Arkansas)

MedianPipes: An FPGA based Highly Pipelined and Scalable Technique for Median Filtering Umer I. Cheema (University of Illinois at Chicago), Gregory Nash (Altera Corporation), Rashid Ansari (University of Illinois at Chicago), Ashfaq A. Khokhar (Illinois Institute of Technology)

Toward Wave Digital Filter based Analog Circuit Emulation on FPGA

Wei Wu (University of California, Los Angeles), Peng Gu (Tsinghua University),

Yen-Lung Chen, Chien-Nan Liu (National Central University), Sudhakar Pamarti (University of California, Los Angeles), Chang Wu (Fudan University), Lei He (University of California, Los Angeles)

Optimized Fixed-Point FPGA Implementation of SVPWM for a Two-Level Inverter Danyal Mohammadi, Said Ahmed-Zaid, Nader Rafla (Boise State University)

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Area Optimization of Arithmetic Units by Component Sharing for FPGAs

Shao Lin Tang, Guy Lemieux (University of British Columbia)

Customizable and High Performance Matrix Multiplication Kernel on FPGA

Jie Wang (Tsinghua University), Jason Cong (University of California, Los Angeles)

Accelerating Complete Decision Support Queries Through High-Level Synthesis Technology Gorker Alp Malazgirt (Bogazici University), Nehir Sonmez (Barcelona Supercomputing Center), Arda Yurdakul (Bogazici University), Osman Unsal, Adrian Cristal (Barcelona Supercomputing Center)

FPGA Acceleration of Irregular Iterative Computations Using Criticality-Aware Dataflow

Optimizations

Siddhartha, Nachiket Kapre (Nanyang Technological University)

On Implementation of LUT with Large Numbers of Inputs

Masahiro Fujita (University of Tokyo)

Design of a Loeffler DCT Using Xilinx Vivado HLS

Seung Yeol Baik, Seokjin Jeong (Korea University), Hyeong-Cheol Oh (Korea University at SeJong)

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