FPGA 2002

Final Program

Tenth ACM International Symposium on Field-Programmable Gate Arrays

Monterey Beach Hotel
Monterey, California
February 24-26, 2002

SUMMARY:

Join us at the beach in Monterey, California for the tenth ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA2002), the premier forum for novel work in all areas related to FPGA technology. This year’s FPGA Symposium features twenty-six papers describing cutting-edge FPGA work. Authors present novel work on FPGA architecture from commercial vendors, research labs and universities. Innovative software research highlights high-speed and high-quality FPGA design. Papers also describe novel devices and software for reconfigurable computing. Finally, FPGA 2002 showcases some very impressive applications of FPGAs.

FPGA2002 provides a relaxed environment for informal information exchange, networking and stimulating discussions with the leaders in FPGA research and development from academia and industry. Paper sessions are separated by ample time to peruse the poster presentations and discuss the latest-breaking FPGA news. This year, FPGA 2002 moves back to the Montery Beach Hotel, a stunning setting guaranteed to facilitate informal discussion as well as formal presentations.

To celebrate our anniversary, the FPGA 2002 dinner banquet will be held at the world-renowned Monterey Bay Aquarium. This is an opportunity not to be missed.

If you are at all interested in FPGA technology and developments, you won’t want to miss this event.

ORGANIZATION: 

General Chair: Martine Schlag, UCSC
Finance Chair: Scott Hauck, U. of Washington
Program Chair: Steve Trimberger, Xilinx
Publicity Chair: Russ Tessier, U. Mass.-Amherst

Program Committee:

Ray Andraka, Andraka Consulting Mike Bershteyn, Cognigine Vaughn Betz, Altera Richard Cliff, Altera Jason Cong, UCLA Andre Dehon, Caltech Eugene Ding, Agere Systems Marty Emmert, Wright State U. Scott Hauck, U. of Washington Rajeev Jayaraman, Xilinx Sinan Kaptanoglu, Adaptive Silicon

Tom Kean, Algotronix Arun Kundu, Actel Miriam Leeser, Northeastern U. Wayne Luk, Imperial College Margaret Marek-Sadowska, UCSB Martine Schlag, UCSC Herman Schmit, CMU Russ Tessier, U. Mass. - Amherst Steve Trimberger, Xilinx Steve Wilton, U. British Columbia Martin Wong, U. Texas

SUPPORT: 

Sponsored by ACM SIGDA, with support from Xilinx, Altera, Actel, and Cypress Semiconductor.

PROGRAM: 

Sunday, February 24, 2002

6:00PM	Registration
7:00PM	Welcoming Reception

Monday, February 25, 2002

7:30AM	Continental Breakfast and Registration
8:20AM	Opening remarks: Martine Schlag, Steve Trimberger

Session 1. Interconnect Architecture

Chair: Steve Wilton, University of British Columbia

8:30AM	Interconnect Enhancements for a High-Speed PLD Architecture, Michael Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh Patel, Bruce Pedersen, Jay Schleicher, Sergey Shumarayev, Altera
8:50AM	FPGA Switch Block Layout and Evaluation, Herman Schmit, Vikas Chandra, Carnegie Mellon
9:10AM	Circuit Design of FPGA Routing Switches, Guy G. Lemieux, David M. Lewis, University of Toronto
9:30AM	Poster Presentations

Session 2. Arithmetic

Chair: Tom Kean, Algotronix

10:30AM	A Faster Distributed Arithmetic Architecture for FPGAs, Radhika S. Grover, Weijia Shang, Qiang Li, Santa Clara University
10:50AM	Efficient Architectures for Implementing Montgomery Modular Multiplication and RSA Modular Exponentiation on Reconfigurable Logic, Alan Daly, Liam Marnane, University College, Cork
11:10AM	A Flexible Floating-Point Format for Optimizing Data-Paths and Operators in FPGA Based DSPs, J. Dido, N. Geraudie, L. Loiseau, O. Payeur, Y. Savaria, École Polytechnique de Montréal; D. Poirier, Miranda Technologies, Inc.
11:30AM	Poster Presentations.

12:00PM

Lunch

Session 3. Physical Design

Chair: Russ Tessier, University of Massachusetts - Amherst

1:30PM	Efficient Circuit Clustering for Area and Power Reduction in FPGAs, Amit Singh, Malgorzata Marek-Sadowska, University of California, Santa Barbara
1:50PM	Integrated Retiming and Placement for Field Programmable Gate Arrays, Deshanand P. Singh, Stephen D. Brown, University of Toronto
2:10PM	SPFD-Based Global Rewiring, Jason Cong, Yizhou Lin, Wangning Long, University of California, Los Angeles
2:30PM	Eve: A CAD Tool for Manual Placement and Pipelining Assistance of FPGA Circuits, William Chow, Jonathan Rose, University of Toronto
2:50PM	Coffee Break and Poster Presentations

Session 4. Cellular and Cryptographic Applications

Chair: Scott Hauck, University of Washington

3:50PM	Application of FPGA Technology to Accelerate the Finite-Difference Time-Domain (FDTD) Method, Ryan N. Schneider, Laurence E. Turner, Michal M. Okoniewski, University of Calgary
4:10PM	FPGA Implementation of Neighborhood-of-Four Cellular Automata Random Number Generators, Barry Shackleford, Motoo Tanaka, Richard J. Carter, Greg Snider, Hewlett-Packard
4:30PM	Cryptographic Rights Management of FPGA Intellectual Property Cores, Tom Kean, Algotronix.

4:50PM

Poster Presentations

6:30AM	Busses Depart for Monterey Bay Aquarium
7:00 PM - 11:00 PM	Dinner at the Monterey Bay Aquarium

Tuesday, February 26, 2002

7:30AM

Continental Breakfast and Registration

Session 5. Synthesis, Verification and Test

Chair: Jason Cong, UCLA

8:30AM	Constrained Clock Shifting for Field Programmable Gate Arrays, Deshanand P. Singh, Stephen D. Brown, University of Toronto
8:50AM	Timing Verification of Dynamically Reconfigurable Logic for the Xilinx Virtex FPGA Series, Ian Robertson, University of Strathclyde; David Robinson, The Alba Centre; James Irvine, University of Strathclyde
9:10AM	FPGA Test Time Reduction Through a Novel Interconnect Testing Scheme, Stuart McCracken, Zeljko Zelic, McGill University
9:30AM	Coffee Break and Poster Presentations.

Session 6. Architecture Analysis and Automation

Chair: Vaughn Betz, Altera

10:30AM	On the Sensitivity of FPGA Architectural Conclusions to Experimental Assumptions, Tools and Techniques, Andy Yan, Rebecca Cheng, Steven Wilton, University of British Columbia
10:50AM	Dynamic Power Consumption in Virtex-II FPGA Family, Li Shang, Princeton University; Alireza S. Kaviani, Kusuma Bathala, Xilinx, Inc..
11:10AM	Automatic Layout of Domain-Specific Reconfigurable Subsystems for System-on-a-Chip, Shawn Phillips, Scott Hauck, University of Washington
11:30AM	Poster Presentations.

12:00PM

Lunch

Session 7. Software for Reconfigurable Systems

Chair: Miriam Leeser, Northeastern University

1:30PM	Performance-Constrained Pipelining of Software Loops onto Reconfigurable Hardware, Greg Snider, Hewlett-Packard
1:50PM	Configuration Prefetching Techniques for Partial Reconfigurable Coprocessor with Relocation and Defragmentation, Zhiyuan Li, Northwestern University; Scott Hauck, University of Washington
2:10PM	Analysis of Quasi-Static Scheduling Techniques in a Virtualized Reconfigurable Machine, Yury Markovskiy, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, University of California Berkeley; André DeHon, Caltech; John Wawrzynek, University of California, Berkeley
2:30PM	Incremental Reconfiguration of Multi-FPGA Systems, K.K. Lee, Synopsys; D.F. Wong, University of Texas at Austin
2:50PM	Coffee Break and Poster Presentations

Session 8. Innovative Applications

Chair: Ray Andraka, Andraka Consulting Group

3:50PM	Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging, Srdjan Coric, Miriam Leeser, Eric Miller, Northeastern University; Marc Trepanier, Mercury Computer Systems
4:10PM	A Dynamically Reconfigurable Adaptive Viterbi Decoder, Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne Burleson, University of Massachusetts, Amherst.
4:30PM	Data Transformations Engines for the Next Generation of System-On-A-Chip FPGAs, Pedro Diniz, Joonseok Park, University of Southern California/ISI
4:50PM	Closing Remarks, Martine Schlag, Steve Trimberger