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FPGA 2001

Final Program

Ninth ACM International Symposium on Field-Programmable Gate Arrays

Doubletree Hotel
Monterey, California
February 11-13, 2001

SUMMARY: Join us for the ninth ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2001), the premier forum for novel work in all areas related to FPGA technology. This year’s symposium features twenty-four papers and twenty-three poster presentations describing cutting-edge FPGA research. Authors from universities, research laboratories and commercial vendors present new work on topics ranging from applications and reconfigurable computing to device architecture and design tools. An entire session is devoted to applications in image and video compression. Paper sessions are separated by ample time to peruse the poster presentations and discuss the latest FPGA news.

The panel this year addresses the question of what FPGAs will look like in the era of systems-on-a-chip. Is it now clear that programmable logic should be combined with ASICs and microprocessors? How should they be combined? What tools are needed to support these devices?

FPGA 2001 provides a relaxed atmosphere for informal information exchange, networking and stimulating discussions with the leaders in FPGA research and development from industry and academia as well as the next generation of FPGA researchers.

If you are at all interested in FPGA technology and developments, you won't want to miss this event.

ORGANIZATION: 
General Chair: Scott Hauck, U. of Washington
Finance Chair: Steve Trimberger, Xilinx
Program Chair: Martine Schlag, UCSC
Publicity Chair: Russ Tessier, U. Mass.-Amherst

Program Committee:

Ray Andraka, Andraka Consulting
Mike Bershteyn, Quickturn
Richard Cliff, Altera
Jason Cong, UCLA
Andre Dehon, Caltech
Eugene Ding, Agere Systems
Carl Ebeling, U. of Washington
Scott Hauck, U. of Washington
TingTing Hwang, Natl. Tsing Hua U.
Sinan Kaptanoglu, Adaptive Silicon
Tom Kean, Algotronix
Arun Kundu, Actel
Miriam Leeser, Northeastern U.
Wayne Luk, Imperial College
Margaret Marek-Sadowska, UCSB
Jonathan Rose, U. of Toronto
Martine Schlag, UCSC
Herman Schmit, CMU
Charles Stroud, UNC - Charlotte
Russ Tessier, U. Mass. - Amherst
Steve Trimberger, Xilinx
Steve Wilton, U. British Columbia
SUPPORT:  Sponsored by ACM SIGDA, with support from Altera, Xilinx, Agere Systems, Cypress and Actel.
PROGRAM: 

Sunday, February 11, 2001

6:00PM

Registration

7:00PM

Welcoming Reception

Monday, February 12, 2001

7:30AM

Continental Breakfast and Registration

8:20AM

Opening remarks: Scott Hauck, Martine Schlag

Session 1. Placement and Routing

Chair: Carl Ebeling, University of Washington

8:30AM

Timing-Driven Placement for Hierarchical Programmable Logic Devices. Michael Hutton, Khosrow Adibasmii and Andrew Leaver, Altera Corporation.

8:50AM

LRoute: A Delay Minimal Router for Hierarchical CPLDs. K. K. Lee, Synopsys; Martin D. F. Wong, University of Texas at Austin.

9:10AM

A Crosstalk-Aware Timing-Driven Router for FPGAs. Steven J. E. Wilton, University of British Columbia.

9:30AM

Runtime and Quality Tradeoffs in FPGA Placement and Routing. Chandra Mulpuri and Scott Hauck, University of Washington.

9:50AM

Coffee Break and Poster Presentations.

Session 2. Technology Mapping

Chair: Steven Wilton, University of British Columbia

10:50AM

Performance-Driven Mapping for CPLD Architectures. Deming Chen, Jason Cong, Milos Ercegovac and Zhijun Huang, University of California, Los Angeles.

11:10AM

Simultaneous Logic Decomposition with Technology Mapping in FPGA Designs. Gang Chen and Jason Cong, University of California, Los Angeles.

11:30AM

Poster Presentations.

12:00PM

Lunch

Session 3. Routing Architectures

Chair: Tom Kean, Algotronix

1:30PM

Using Sparse Crossbars within LUT Clusters. Guy G. Lemieux and David M. Lewis, University of Toronto.

1:50PM

Detailed Routing Architectures for Embedded Programmable Logic IP Cores. Peter Hallschmid and Steven J.E. Wilton, University of British Columbia.

2:10PM

Mixing Buffers and Pass Transistors in FPGA Routing Architectures. Mike Sheng and Jonathan Rose, University of Toronto.

2:30PM

Coffee Break and Poster Presentations.

Session 4. Applications

Chair: Ray Andraka, Andraka Consulting

3:30PM

Reprogrammable Network Packet Processing on the Field Programmable Port Extender (FPX). John W. Lockwood, Naji Naufel, David E. Taylor and Jon S. Turner, Washington University.

3:50PM

Fast Implementations of secret-key block ciphers using mixed inner- and outer-round pipelining. Pawel Chodowiec, Po Khuon, and Kris Gaj, George Mason University

4:10PM

Algorithmic Transformations in the Implementation of K-means Clustering on Reconfigurable Hardware. Mike Estlick, Miriam Leeser, Northeastern University; John J. Szymanski and James Theiler, Los Alamos National Laboratory.

6:00PM

Dinner

Panel: Is marriage in the cards for programmable logic, microprocessors, and ASICs?

Moderator: Sinan Kaptanoglu, Adaptive Silicon

Panelists: John East, Actel
Tim Garverick, Adaptive Silicon
Scott Hauck, University of Washington
David Papworth, Intel
Danesh Tavana, Triscend
Steve Trimberger, Xilinx
Ronnie Vasishta, LSI Logic

The panelists focus first on the possibility, likelihood or inevitability of combinations of programmable logic, microprocessors and ASICs in a single chip and then address the following issues:

Will they be as general as possible or application specific?

Will all three types of logic be involved, or perhaps only two?

How much of the die area should be allocated to programmable logic?

How will the CAD tools cope with the speed mismatch between the programmable logic and fixed logic on the same chip?

How will the designs be partitioned into programmable and fixed parts; will it be done by humans or by CAD tools?

These future predictions may depend on the system design size: are the answers for 500K gate system designs different from those for 5,000K gate system designs? What will happen when 50,000K gate system designs become common-place in 5 years?

Tuesday, February 13, 2001

7:30AM

Continental Breakfast and Registration

Session 5. Reconfigurable Computing Applications

Chair: Steve Trimberger, Xilinx

8:30AM

Attacking the Semantic Gap Between Application Programming Languages and Configurable Hardware. Greg Snider, Barry Shackleford and Richard J. Carter, Hewlett-Packard Laboratories.

8:50AM

Matching and Searching Analysis for Parallel Hardware Implementation on FPGAs. Pablo Moisset, Pedro Diniz and Joonseok Park, University of Southern California/Information Sciences Institute.

9:10AM

Evaluation of the Streams-C C-to-FPGA Compiler: An Applications Perspective. Janette Frigo, Maya Gokhale and Dominique Lavenier, Los Alamos National Laboratory.

9:30AM

The Effect of Reconfigurable Units in Superscalar Processors. Jorge E. Carrillo and Paul Chow, University of Toronto.

9:50AM

Coffee Break and Poster Presentations.

 

 

Session 6. Pipelined Routing Architectures

Chair: Andre Dehon, Cal Tech

10:50AM

Interconnect Pipelining in a Throughput-Intensive FPGA Architecture. Amit Singh, Arindam Mukherjee and Malgorzata Marek-Sadowska, University of California, Santa Barbara.

11:10AM

The Case for Registered Routing Switches in Field Programmable Gate Arrays. Deshanand P. Singh and Stephen D. Brown, University of Toronto.

11:30AM

Poster Presentations.

12:00PM

Lunch

Session 7. Issues in FPGA-Based Systems

Chair: Charles Stroud, University of North Carolina - Charlotte

1:30PM

Configuration Compression for FPGA-based Embedded Systems. Andreas Dandalis and Viktor K. Prasanna, University of Southern California.

1:50PM

A Memory Coherence Technique for Online Transient Error Recovery of FPGA Configurations. Wei-Je Huang and Edward J. McCluskey, Stanford University.

2:10PM

Run-Time Defect Tolerance using JBits. Prasanna Sundararajan and Steven A. Guccione, Xilinx Corporation.

2:30PM

Coffee Break and Poster Presentations.

Session 8. Applications in Image/Video Compression

Chair: Miriam Leeser, Northeastern University

3:30PM

A pipelined architecture for partitioned DWT based lossy image compression using FPGAs. Jörg Ritter and Paul Molitor, Martin-Luther University.

3:50PM

An FPGA-Based Video Compressor for H.263 Compatible Bitstreams. G. Lienhart, R. Lay, K.H. Noffz and R. M"anner, University of Mannheim.

4:10PM

FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression. S. Ramachandran and S. Srinivasan, Indian Institute of Technology, Chennai.

4:30PM

Closing Remarks: Scott Hauck, Martine Schlag