Stephen Ibanez (Stanford University), email: email@example.com
P4 has emerged as the de facto standard language for describing how network packets should be processed, and is becoming widely used by network owners, systems developers, researchers and in the classroom. The goal of this tutorial is to teach engineers, researchers, and students how to program using P4, and to build prototypes running on real hardware. Our target is the NetFPGA SUME platform, a 4x10 Gb/s PCIe card designed for use in universities for teaching and research. Until now, NetFPGA users have needed to learn an HDL such as Verilog or VHDL, making it off limits to many software developers and students. Therefore, we developed the P4->NetFPGA workflow, allowing developers to describe how packets are to be processed in the high-level P4 language, then compile their P4 programs to run at line rate on the NetFPGA SUME board. The P4->NetFPGA workflow is built upon the Xilinx P4-SDNet compiler and the NetFPGA SUME open source code base. In this tutorial, we provide a brief overview of the P4 programming language and describe the P4->NetFPGA workflow. The deep dive session will provide attendees with an opportunity to obtain hand-on experience writing, compiling, and running P4 programs on the SUME board.
Stephen Ibanez is a Ph.D. Candidate at Stanford University, working with Professor Nick McKeown. His research focuses on finding new and exciting applications for high-speed programmable data planes. He has hosted numerous P4-related tutorials at venues such as SIGCOMM, and he is now leading the P4 to NetFPGA community of developers and users.
Chris Lavin (Xilinx Labs), email: firstname.lastname@example.org
RapidWright is a new open source framework from Xilinx Research Labs that provides a bridge to Xilinx Vivado's backend implementation tools. RapidWright works synergistically with Vivado by reading and writing design checkpoint (DCP) files to provide accurate device models, netlist creation/modification, and on-the-fly implementation generation. With this collection of capabilities, RapidWright is setting the groundwork of a new ecosystem aimed at further advancing FPGA tools with the specific target of enabling domain-specific back-end flows.
Attendees of this workshop can expect to: (1) gain a deeper understanding of how to leverage Xilinx architecture, (2) know how to use RapidWright and apply its capabilities in their own designs and (3) learn about design methodologies that can lead to near-spec performance. Several RapidWright tools have been built, among those included in the workshop are:
RapidWright opens a new path for domain-specific implementation tools that will improve performance and productivity and we invite the community to help us further the potential of FPGA technology.
Chris Lavin is a staff engineer in Xilinx Research Labs and is the principal author of RapidWright. His work focuses on FPGA tools and architecture motivated by a desire to improve productivity and performance. Prior to Xilinx, he worked at Tabula, an innovative programmable logic startup and received his PhD from Brigham Young University where he developed the open source framework RapidSmith.