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FPGA 2003Eleventh ACM International Symposium on Field-Programmable Gate Arrays Monterey Beach
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Join us at the beach in FPGA2003 provides a relaxed
environment for informal information exchange, networking and stimulating
discussions with the leaders in FPGA research and development from academia and
industry. Paper sessions are separated by ample time to peruse the poster
presentations and discuss the latest-breaking FPGA news. This year, FPGA 2003 will be at the Monterey
Beach Hotel, a stunning setting guaranteed to facilitate informal discussion as
well as formal presentations. The
FPGA 2003 dinner banquet will be followed by a panel discussion. This is an opportunity not to be missed. If you are interested in
FPGA technology and developments, you won’t want to miss this event. Organization: General Chair:
Steve Trimberger,
Xilinx Program Chair: Russ Tessier,
U. Mass.-Amherst Finance Chair: Martine Schlag, UCSC Publicity Chair: Steve Wilton, U. Panel Chair: Herman Schmit,
CMU Program
Committee:
PROGRAM
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Continental Breakfast and
Registration |
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Opening
Remarks,
Steve Trimberger, Russ Tessier |
Session
1.
Novel Architectures
Chair: Michael Butts, Cadence
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Architectures
and Algorithms for Synthesizable Embedded Programmable Logic Cores, Noha Kafafi, Kimberly Bozman, and Steven J.E. Wilton, University of British Columbia |
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The
Stratix Routing and Logic
Architecture, David Lewis, Vaughn Betz, David Jefferson, Andy Lee,
Chris Lane, Paul Leventis,
Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, and Jonathan Rose, Altera Corporation |
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A
Pipelined Configurable Gate Array for Embedded Processors, Andrea
Lodi, Mario Toma, Fabio Campi, Andrea Cappelli, Roberto Canegallo, and Roberto Guerrieri, University of
Bologna and STMicroelectronics |
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Coffee
Break and Poster Presentations |
Session
2.
Placement
Chair: Vaughn Betz, Altera Corporation
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Hardware-Assisted
Simulated Annealing with Application for Fast FPGA Placement, Michael G.
Wrighton and André DeHon, California Institute of
Technology |
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Parallel
Placement for Field-Programmable Gate Arrays, Pak K.
Chan and Martine D.F. Schlag, University of California, Santa Cruz |
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I/O
Placement for FPGAs with
Multiple I/O Standards, Wai-Kei
Mak, |
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Poster
Presentations |
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Lunch |
Session 3. Routing
Chair:
Jason Cong, UCLA
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Wire
Type Assignment for FPGA Routing, Seokjin Lee, Hua Xiang,
D. F. Wong, Richard Y. Sun, University
of Texas at Austin, UIUC, and Xilinx Corporation |
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PipeRoute: A Pipelining-Aware Router for FPGAs, Akshay Sharma, Carl Ebeling, and Scott Hauck, |
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Stochastic,
Spatial Routing for Hypergraphs,
Trees, and Meshes, Randy Huang, John Wawrzynek,
and André DeHon,
University of California, Berkeley and California Institute of Technology |
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Poster
Presentations |
Session
4. Prototyping,
Verification, and Test
Chair: Majid Sarrafzadeh, UCLA
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Implementation
of BEE: A Real-Time Large-scale Hardware Emulation Engine, Chen
Chang, Kimmo Kuusilinna, Brian Richards, and
Robert W. Brodersen,
University of California, Berkeley and Tampere
University of Technology |
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High-Level
Modeling and FPGA Prototyping of Microprocessors, Joydeep Ray and James C. Hoe, |
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Reducing
Pin and Area Overhead in Fault-Tolerant FPGA-based Designs, Fernanda Gusmão de Lima, Luigi Carro, and Ricardo Reis, Universidade Federal do |
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Poster
Presentations |
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Dinner |
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Panel - Attack of the Killer Gate Arrays Moderator: Michael Butts, Cadence Panelists: Herman Schmit,
Steve Trimberger, Xilinx Jonathan Rose, Altera Ronnie Vasishta,
LSI Logic (others panelists TBD) The ever-growing capacity and speed of FPGAs have brought them into the heart of the silicon
mainstream. Major ASIC vendors have
responded by reviving masterslice gate arrays,
standard prefab die with design-specific metal layers. They claim lower NREs,
quicker delivery and easier design than cell-based ASICs,
and lower unit cost, better speed, capacity and power than FPGAs. Do these gate arrays spell doom for FPGA vendors’
dreams of displacing the ASIC as a mainstream silicon platform? Will the FPGA's high volume, superior
flexibility and time-to-market prevail?
Or will they co-exist in different classes of application? Why?
When? We have assembled a panel of experts from FPGA and
ASIC vendors and academia to duke it out.
Each panelist will give a short presentation
putting forward their point of view, then we'll have
interactive debate among the panelists and
attendees. |
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Breakfast |
Session
5.
Logic Synthesis and Mapping
Chair: Steve Wilton,
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Placement-driven
Technology Mapping for LUT-based FPGAs, Jason
Cong, Ashok Jaganathan, and Joey Y.
Lin, UCLA |
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Verifying
the Correctness of FPGA Logic Synthesis Algorithms, Boris Ratchev, Mike Hutton, Gregg Baeckler, and Babette van Antwerpen,
Altera Corporation |
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Using
Logic Duplication to Improve Performance in FPGAs, Karl Schabas and Stephen D. Brown, |
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Coffee
Break and Poster Presentations |
Session
6. Device-Level
Design
Chair: Guy Lemieux,
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A
Scalable 2V, 20 GHz FPGA using SiGe
HBT BiCMOS Technology, J.R. Guo, C. You, K. Zhou, M. Chu, B.S. Goda, R.P. Kraft, and J.F. McDonald, Rensselaer
Polytechnic Institute |
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Design of
FPGA Interconnect for Multilevel Metalization, Raphael Rubin
and André DeHon,
California Institute of Technology |
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Automatic Transistor and Physical
Design of FPGA Tiles from an Architectural Specification, Ketan Padalia, Ryan Fung, Mark Bourgeault,
Aaron Egier, and Jonathan
Rose, University of Toronto |
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Poster
Presentations |
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Lunch |
Session
7. Architecture
Analysis and Evaluation
Chair: Sinan Kaptanoglu, Altera Corporation
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Architecture
Evaluation for Power-Efficient FPGAs,
Fei Li, Deming
Chen, Lei He, and Jason Cong, UCLA |
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Post-Placement
C-slow Retiming for the Xilinx Virtex FPGA, Nicholas Weaver, Yury Markovskiy, Yatish
Patel, and John Wawrzynek,
University of California, Berkeley |
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An
FPGA Architecture with Enhanced Datapath Functionality, Katarzyna Leijten-Nowak and Jef L. van Meerbergen, Eindhoven
University of Technology and Philips Research Labs |
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Coffee
Break and Poster Presentations |
Session
8. Innovative
Applications
Chair: Ray Andraka,
Andraka Consulting Group
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A
Fully Pipelined Memoryless
17.8 Gbps AES-128 Encryptor, Kimmo U. Järvinen, Matti
T. Tommiska and Jorma O. Skyttä,
Helsinki University of Technology |
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Methodology
to Implement Block Ciphers in Reconfigurable Hardware and its Application to
Fast and Compact AES RIJNDAEL, Francois-Xavier Standaert, Gael Rouvroy, Jean-Jacques Quisquater, and Jean-Didier Legat, Université Catholique de Louvain |
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Energy-Efficient
Signal Processing Using FPGAs, Seonil Choi, Ronald Scrofano, Viktor K. Prasanna, and Ju-wook Jang, University of Southern California |
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Closing
Remarks, Steve Trimberger, Russ Tessier |