Program of FPGA 2016

24th Annual International Symposium on Field Programmable Gate Arrays, February 21 – 23, 2016

Sunday, February 21

All sessions held in San Carlos Room 1-3 unless otherwise noted.

Int’l Workshop on Overlay Architectures for FPGAs (OLAF)

9:00       Welcome, Hayden Kwok-Hay So (Univ. Hong Kong), John Wawrzynek, (Univ. California, Berkeley)

9:10       Paper presentations

Lunch and Panel Discussion (Ferrantes Room, 10th Floor)

12:00     Lunch

12:15     Panel Discussion: "I need that last MHz of performance, take that overlay away!"

Jan Gray (Gray Research LLC), Guy Lemieux (Univ. British Columbia), Hayden So (Univ. Hong Kong), Steve Trimberger (Xilinx), Peter Yiannacouras (Altera)

1:15       Break

FPGA 2016 Designer / Tutorial Sessions

1:30       Welcome, Stephen Neuendorffer (Xilinx)

Session D1: Hardware Features

Chair: Lesley Shannon (Simon Fraser Univ.)

1:35       HyperPipelining of High-Speed Interface Logic

Gregg Baeckler (Altera)

2:25       Spatial Debug and Debug without Re-programming in FPGAs

Pankaj Shanker (Microsemi)

2:50       Break and Demos (San Carlos Foyer)

Session D2: System Level Methodology

Chair: Graham Schelle (Xilinx)

3:00       SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC

Vinod Kathail, James Hwang, Welson Sun, Yogesh Chobe, Tom Shui, Jorge Carrillo (Xilinx)

3:50       FCUDA-SoC: Platform Integration for Field-Programmable SoC with the CUDA-to-FPGA Compiler

Tan Nguyen, Swathi Gurumani, Kyle Rupnow (Advanced Digital Sciences Center), Deming Chen (Univ. Illinois at Urbana-Champaign)

4:15       Agile Co-design for a Reconfigurable Datacenter

Eric Chung (Microsoft)

4:40       Wrap up

4:45       Demos (San Carlos Foyer)

FPGA 2016 Reception

7:00       Reception (Ferrantes Room, 10th Floor)

Monday, February 22

All sessions held in San Carlos Room 1-3 unless otherwise noted.

8:00       Continental Breakfast (San Carlos Foyer)

8:45       Opening Remarks, Deming Chen (Univ. Illinois at Urbana-Champaign), Jonathan Greene (Microsemi)

Session 1: Neural Networks and OpenCL

Chair: Jason Anderson (Univ. Toronto)                                                                                             

9:05       Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks

Naveen Suda (Arizona State Univ.), Vikas Chandra, Ganesh Dasika (ARM.), Abinash Mohanty, Yufei Ma, Sarma Vrudhula, Jae-sun Seo, Yu Cao (Arizona State Univ.)

9:30       Going Deeper with Embedded FPGA Platform for Convolutional Neural Network  [Demo Video]

Jiantao Qiu, Jie Wang, Song Yao, Kaiyuan Guo, Boxun Li, Erjin Zhou, Jincheng Yu, Tianqi Tang (Tsinghua Univ.), Ningyi Xu (Microsoft Research Asia), Sen Song, Yu Wang, Huazhong Yang (Tsinghua Univ.)

9:55       Using Stochastic Computing to Reduce the Hardware Requirements for a Restricted Boltzmann Machine Classifier (short)

Bingzhe Li, M. Hassan Najafi, David J Lilja (Univ. Minnesota, Twin Cities)

10:00      A Platform-Oblivious Approach for Heterogeneous Computing: a Case Study with Monte Carlo-based Simulation for Medical Applications (short)

Shih-Hao Hung, Min-Yu Tsai, Bo-Yi Huang, Chia-Heng Tu (National Taiwan Univ.)

10:05     A Case for Work-stealing on FPGAs with OpenCL Atomics (short)

Nadesh Ramanathan, John Wickerson, Felix Winterstein, George A Constantinides (Imperial College)

Poster Session 1 (San Carlos Room 4)

10:10     See list below; authors of short papers from Session 1 will also be available for discussion.

Session 2: Cooling and Clocking

Chair: Peter Cheung (Imperial College)

11:10     Physical Design of 3D FPGAs Embedded with Micro-channel-based Fluidic Cooling

Zhiyuan Yang, Ankur Srivastava (Univ. Maryland, College Park)

11:35     Stratix™ 10 High Performance Routable Clock Networks

Carl Ebeling, Dana How, David Lewis, Herman Schmit (Altera)

12:00     Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network (short)

Henri Fraisse, Abhishek Joshi, Dinesh Gaitonde, Alireza Kaviani (Xilinx)

Lunch (Ferrantes Room, 10th Floor)

12:05     Lunch

Session 3: Circuit Design, Graph Processing Applications

Chair: Mike Hutton (Altera)

1:45       FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures

Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne (EPFL)

2:10       Towards PVT-Tolerant Glitch-Free Operation in FPGAs

Safeen Huda, Jason Anderson (Univ. Toronto)

2:35       Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement (short)

Timothy A. Linscott (Seattle Univ.), Benjamin Gojman, Raphael Rubin, Andre DeHon (Univ. Pennsylvania)

2:40       FPGP: Graph Processing Framework on FPGA (short)

Guohao Dai, Yuze Chi, Yu Wang, Huazhong Yang (Tsinghua Univ.)

2:45       GraphOps: A Dataflow Library for Graph Analytics Acceleration (short)

Tayo Oguntebi, Kunle Olukotun (Stanford Univ.)

Poster Session 2 (San Carlos Room 4)

2:50       See list below; authors of short papers from Sessions 2 and 3 will also be available for discussion.

Session 4: Applications and System-level Tools

Chair: Kyle Rupnow (Advanced Digital Sciences Center)

3:50       High Performance Linkage Disequilibrium: FPGAs Hold the Key

Nikolaos Alachiotis, Gabriel Weisz (Carnegie Mellon Univ.)

4:15       LMC: Automatic Resource-Aware Program-Optimized Memory Partitioning

Hsin-Jung Yang (MIT), Kermin Fleming, Michael Adler (Intel), Felix Winterstein (Imperial College), Joel Emer (MIT)

4:40       Efficient Memory Partitioning for Parallel Data Access via Data Reuse

Jincheng Su, Fan Yang, Xuan Zeng (Fudan Univ.), Dian Zhou (Univ. Texas at Dallas)

5:05       Break

Banquet and Panel Discussion (Ferrantes Room, 10th Floor)

6:30       Banquet

7:00       Panel Discussion: “Intel Acquires Altera: How Will the World of FPGAs be Affected?”

Derek Chiou (Moderator), Microsoft and Univ. Texas at Austin

Hemant Dhulla, VP of Data Center and Wired Communication, Xilinx

Alex Grbic, VP of Product Marketing & Planning, Intel Programmable Solutions Group (formerly Altera)

Prabhat (PK) Gupta, Director of Cloud Platform Technology, Intel

H. Peter Hofstee, Distinguished Research Staff Member, IBM

Rick Merritt, Silicon Valley Bureau Chief, EE Times

Tuesday, February 23

All sessions held in San Carlos Room 1-3 unless otherwise noted.

8:00       Continental Breakfast (San Carlos Foyer)

Session 5: Architecture and Tools

Chair: Jonathan Rose (Univ. Toronto)

9:00       PRFloor: An Automatic Floorplanner for Partially Reconfigurable FPGA Systems

Tuan D. A. Nguyen (National Univ. Singapore), Akash Kumar (Technische Universität Dresden)

9:25       The Stratix™ 10 Highly Pipelined FPGA Architecture

David Lewis, Gordon Chiu, Jeffrey Chromczak, David Galloway, Ben Gamsa, Valavan Manohararajah, Ian Milton, Tim Vanderhoek, John Van Dyken (Altera)

9:50       Case for Design-Specific Machine Learning in Timing Closure of FPGA Designs (short)

Que Yanghua, Chinnakkannu Adaikkala Raj (Nanyang Technological Univ.),  Harnhua Ng, Kirvy Teo (Plunify), Nachiket Kapre (Nanyang Technological Univ.)

9:55       Just In Time Assembly of Accelerators (short)

Sen Ma, Zeyad Aklah, David Andrews (Univ. Arkansas)

10:00     CASK - Open-Source Custom Architectures for Sparse Kernels (short)

Paul Grigoras, Pavel Burovskiy, Wayne Luk (Imperial College)

Poster Session 3 (San Carlos Room 4)

10:05     See list below; authors of short papers from Session 5 will also be available for discussion.

Session 6: System-Level Tools

Chair: Mingie Lin (Univ. Central Florida)

11:00     GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths

Nachiket Kapre, Deheng Ye (Nanyang Technological Univ.)

11:25     Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis

Janarbek Matai, Dustin Richmond, Dajung Lee, Zac Blair, Qiongzhi Wu, Amin Abazari, Ryan Kastner (Univ. California, San Diego)

11:50     SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing [Please contact the authors for their slides]

Michael Wirthlin, Andrew Keller, Chase McCloskey, Parker Ridd (Brigham Young Univ.), David Lee (Sandia National Laboratories), Jeffrey Draper (Univ. Southern California)

Lunch (Ferrantes Room, 10th Floor)

12:15     Lunch

Session 7: High-level Synthesis and Tools

Chair: David Biancolin (Univ. California at Berkeley)

1:55       Optimal Circuits for Streamed Linear Permutations Using RAM

François Serre, Thomas Holenstein, Markus Püschel (ETH Zurich)

2:20       High Level Synthesis of Complex Applications:An H.264 Video Decoder

Xinheng Liu (Univ. Illinois at Urbana-Champaign), Yao Chen (Nankai Univ.), Tan Nguyen, Swathi Gurumani, Kyle Rupnow (Advanced Digital Sciences Center), Deming Chen (Univ. Illinois at Urbana-Champaign)

2:45       Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis

Xitong Gao, John Wickerson, George A. Constantinides (Imperial College)

3:10       Break

Session 8: Applications

Chair: George Constantinides (Imperial College)

3:30        Reducing Memory Requirements for High-Performance and Numerically Stable Gaussian Elimination

David Boland (Monash Univ.)

3:55       FGPU: An SIMT-Architecture for FPGAs

Muhammed Al Kadi, Benedikt Janssen, Michael Huebner (Ruhr Univ. Bochum)

4:20       A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems

Gabriel Weisz, Joseph Melber, Yu Wang (Carnegie Mellon Univ.), Kermin Fleming, Eriko Nurvitadhi (Intel), James C. Hoe (Carnegie Mellon Univ.)

4:45       Best Paper Award and Close of Conference 

List of Posters By Session

Poster Session 1

A Low DDR Bandwidth 100FPS 1080p Video 2D Discrete Wavelet Transform Implementation on FPGA

Mohammed Shaaban Ibraheem, Syed Zahid Ahmed, Khalil Hachicha (Sorbonne Universités, UPMC Paris 06), Sylvain Hochberg (CIRA), Patrick Garda (Sorbonne Universités, UPMC Paris 06)

A Scalable Heterogeneous Dataflow Architecture for Big Data Analytics Using FPGAs

Ehsan Ghasemi, Paul Chow (Univ. Toronto)

Accelerating Database Query Processing on OpenCL-based FPGAs

Zeke Wang, Huiyan Cheah, Johns Paul, Bingsheng He, Wei Zhang (Nanyang Technological Univ.)

An Improved Global Stereo-Matching on FPGA for Real-Time Applications

Daolu Zha, Xi Jin, Tian Xiang (Univ. Science of Technology of China)

ENFIRE: An Energy-efficient Fine-grained Spatio-temporal Reconfigurable Computing Fabric

Wenchao Qian, Christopher Babecki, Robert Karam, Swarup Bhunia (Case Western Reserve Univ.)

Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA

Pingakshya Goswami, Dinesh Bhatia (Univ. Texas at Dallas)

Increasing the Utility of Self-Calibration Methods in High-Precision Time Measurement Systems

Matthias Hinkfoth, Ralf Salomon (Univ. Rostock)

Knowledge is Power: Module-level Sensing for Runtime Optimisation

James Davis, Eddie Hung, Joshua Levine, Edward Stott, Peter Cheung, George Constantinides (Imperial College)

Machine-Learning driven Auto-Tuning of High-Level Synthesis for FPGAs

Li Ting, Harri Sapto Wijaya, Nachiket Kapre (Nanyang Technological Univ.)

Re-targeting Optimization Sequences from Scalar Processors to FPGAs in HLS compilers

Ronak Kogta, Suresh Purini, Ajit Mathew (Int’l Institute of Information Technology)

Poster Session 2

A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS

Jie Lei (Xidian Univ. & UCLA), Yuting Chen (UCLA), Yunsong Li (Xidian Univ.), Jason Cong (UCLA)

An Activity Aware Placement Approach For 3D FPGAs

Girish Deshpande, Dinesh Bhatia (Univ. Texas at Dallas)

An Extensible Heterogeneous Multi-FPGA Framework for Accelerating N-body Simulation

Tianqi Wang, Bo Peng, Xi Jin (Univ. Science and Technology of China)

An FPGA-Based Controller for a 77 GHz MEMS Tri-Mode Automotive Radar

Sabrina Zereen (Invotek Electronics Inc), Sundeep Lal (VerifEye Technologies), Mohammed Khalid, Sazzadur Chowdhury (Univ. Windsor)

An FPGA-SOC Based Accelerating Solution for N-body Simulations in MOND

Bo Peng, Tianqi Wang, Xi Jin (School of Physical Sciences, USTC), Chuanjun Wang (Chinese Academy of Sciences)

Automated Verification Code Generation in HLS Using Software Execution Traces

Liwei Yang (Nanyang Technological Univ.), Swathi Gurumani (Advanced Digital Sciences Center), Suhaib Fahmy (Nanyang Technological Univ.), Deming Chen (Univ. Illinois at Urbana-Champaign), Kyle Rupnow (Advanced Digital Sciences Center)

DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA

Jing Ye, Yu Hu, Xiaowei Li (State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences)

Evaluating the Impact of Environmental Factors on Physically Unclonable Functions

Sebastien Bellon (ALaRI - USI), Claudio Favi (Nagra), Miroslaw Malek (ALaRI - USI), Marco Macchetti (Nagra), Francesco Regazzoni (ALaRI - USI)

Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology

Yu Bai, Mingjie Lin (Univ. Central Florida)

Testing FPGA Local Interconnects Based on Repeatable Configuration Modules

Zhen Yang, Jian Wang, Meng Yang, Jinmei Lai (Fudan Univ.)

Poster Session 3

A 1 GSa/s, Reconfigurable Soft-core FPGA ADC

Stefan Visser, Harald Homulle, Edoardo Charbon (TU Delft)

A Full-Capacity Local RoutingArchitecture for FPGAs

Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli (EPFL)

ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture

Yu-Ting Chen, Jason Cong, Zhenman Fang, Peipei Zhou (UCLA)

Doubling FPGA Throughput via a Soft SerDes Architecture for Full-Bandwidth Serial Pipelining

Aaron Landy, Greg Stitt (Univ. Florida)

Enhanced TERO-PUF Implementations and Characterization on FPGAs

Cédric Marchand, Lilian Bossuet (Laboratoire Hubert Curien, Univ. Lyon), Abdelkarim Cherkaoui (TIMA Laboratory)

FPGA Power Estimation Using Automatic Feature Selection

Yunxuan Yu, Lei He (UCLA)

HGum: Messaging Framework for Hardware Accelerators

Sizhuo Zhang (MIT), Hari Angepat, Derek Chiou (Microsoft)

Low-Swing Signaling for FPGA Power Reduction

Sayeh Sharifymoghaddam, Ali Sheikholeslami (Univ. Toronto)

Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric

Mohammed Alawad, Mingjie Lin (Univ. Central Florida)

t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs

Nimish Agashiwala, Satya Prakash Upadhyay, Kia Bazargan (Univ. Minnesota Twin Cities)